LOW POWER BUFFER WITH GAIN BOOST

• US 20170207864A1
• Filed: 03/31/2017
• Published: 07/20/2017
• Est. Priority Date: 02/04/2015
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Inphi Corporation
• Inventors: TAN, Han-Yuan, GORECKI, James Lawrence
• Granted Patent: US 10,110,204 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 27/026 associated with an amplifier G11C27/028 takes precedence
• CPC Class Codes: H03F 1/3205 in field-effect transistor amplifiers
• CPC Class Codes: H03F 1/3211 in differential amplifiers
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03G 3/20 Automatic control H03G3/005 takes precedence; combined with volume compression or expansion H03G7/00
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 5/023 using field effect transistors
• CPC Class Codes: H03M 1/1215 using time-division multiplexing
• CPC Class Codes: H03M 1/124 Sampling or signal conditioning arrangements specially adapted for A/D converters
• CPC Class Codes: H03M 3/38 Calibration
• CPC Class Codes: H04B 17/21 for calibration; for correcting measurements

Abstract

The present disclosure provides a detailed description of techniques for implementing a low power buffer with gain boost. More specifically, some embodiments of the present disclosure are directed to a buffer with a stacked transistor configuration, wherein the first transistor receives an input signal and the second transistor receives a complement of the input signal. The first transistor is configured to generate a non-inverting response to the input signal, and the second transistor is configured to generate an inverting response to the complement of the input signal, and to generate a negative g_ds effect, enabling the buffer to exhibit low power and unity gain across a wide bandwidth. In other embodiments, the stacked transistor configuration can be deployed in a full differential implementation. In other embodiments, the buffer can include techniques for improving linearity, DC level shifts, capacitive input loading, and output slewing, settling, and drive capabilities.

Claims

1-20. -20. (canceled)

21. A communication system having circuitry for gain boost of an output signal, the communication system comprising:

at least one communication receiver having an analog-to-digital converter comprising a buffer circuit; and

an output node connected to the buffer circuit that drives an output signal to the output node, wherein the buffer circuit comprises;

a current mirror connected to a first supply node, the current mirror to produce a current feedback signal, wherein the current mirror provides a feedback path through the current feedback signal to improve symmetry between positive and negative slewing current at the output signal;

a first transistor coupled to a first input voltage to form a first input signal;

a second transistor coupled to the first input signal and coupled to a second input voltage, the second input voltage being a complement of the first input voltage;

a first bias circuit being coupled to the second transistor and being coupled to a bias voltage; and

a second bias circuit being coupled to the bias voltage, and being coupled to the current feedback signal through at least one transistor.

22. The communication system of claim 21, wherein the at least one transistor of the second bias circuit that is coupled the first input voltage.

23. The communication system of claim 21, wherein both of the first bias circuit and the second bias circuit are controlled by a common connection to the bias voltage.

24. The communication system of claim 21 further comprising one or more variable gain amplifiers for processing at least the first input signal.

25. The communication system of claim 21 wherein the analog-to-digital converter further comprises a plurality of shift and hold registers.

26. The communication system of claim 21 further comprising a phase interpolator module.

27. The communication system of claim 21 wherein the analog-to-digital converter further comprises a plurality of track and hold registers.

28. The communication system of claim 21, wherein the first bias circuit, and the second bias circuit have a respective plurality of design attributes, and wherein at least one of the respective plurality of design attributes is established to achieve a gain equal to a value of one, the value being defined by an output amplitude the output signal divided by an input amplitude of the first input signal.

29. The communication system of claim 21, wherein at least one of the first transistor, or the second transistor, or the first bias circuit, or the second bias circuit comprise an N-type MOSFET device.

30. The communication system of claim 21, wherein the current mirror is further connected to a second supply node.

31. A gain boost buffer circuit for providing gain boost of an output signal, the gain boost buffer circuit comprising:

an output node connected to the gain boost buffer circuit that drives an output signal to the output node, wherein the gain boost buffer circuit comprises;

a current mirror connected to a first supply node, the current mirror to produce a current feedback signal, wherein the current mirror provides a feedback path through the current feedback signal to improve symmetry between positive and negative slewing current at the output signal;

a first transistor coupled to a first input voltage to form a first input signal;

a second transistor coupled to the first input signal and coupled to a second input voltage, the second input voltage being a complement of the first input voltage;

a first bias circuit being coupled to the second transistor and being coupled to a bias voltage; and

a second bias circuit being coupled to the bias voltage, and being coupled to the current feedback signal through at least one transistor.

32. The gain boost buffer circuit of claim 31, wherein the at least one transistor of the second bias circuit that is coupled the first input voltage.

33. The gain boost buffer circuit of claim 31, wherein both of the first bias circuit and the second bias circuit are controlled by a common connection to the bias voltage.

34. The gain boost buffer circuit of claim 31 further comprising one or more variable gain amplifiers for processing at least the first input signal.

35. The gain boost buffer circuit of claim 31, further comprising a plurality of shift and hold registers.

36. The gain boost buffer circuit of claim 31 further comprising a phase interpolator module.

37. The gain boost buffer circuit of claim 31, further comprising a plurality of track and hold registers.

38. The gain boost buffer circuit of claim 31, wherein the first bias circuit, and the second bias circuit have a respective plurality of design attributes, and wherein at least one of the respective plurality of design attributes is established to achieve a gain equal to a value of one, the value being defined by an output amplitude the output signal divided by an input amplitude of the first input signal.

39. The gain boost buffer circuit of claim 31, wherein at least one of the first transistor, or the second transistor, or the first bias circuit, or the second bias circuit comprise an N-type MOSFET device.

40. The gain boost buffer circuit of claim 31, wherein the current mirror is further connected to a second supply node.