LOW POWER BUFFER WITH GAIN BOOST
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Abstract
The present disclosure provides a detailed description of techniques for implementing a low power buffer with gain boost. More specifically, some embodiments of the present disclosure are directed to a buffer with a stacked transistor configuration, wherein the first transistor receives an input signal and the second transistor receives a complement of the input signal. The first transistor is configured to generate a non-inverting response to the input signal, and the second transistor is configured to generate an inverting response to the complement of the input signal, and to generate a negative gds effect, enabling the buffer to exhibit low power and unity gain across a wide bandwidth. In other embodiments, the stacked transistor configuration can be deployed in a full differential implementation. In other embodiments, the buffer can include techniques for improving linearity, DC level shifts, capacitive input loading, and output slewing, settling, and drive capabilities.
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Citations
40 Claims
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1-20. -20. (canceled)
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21. A communication system having circuitry for gain boost of an output signal, the communication system comprising:
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at least one communication receiver having an analog-to-digital converter comprising a buffer circuit; and an output node connected to the buffer circuit that drives an output signal to the output node, wherein the buffer circuit comprises; a current mirror connected to a first supply node, the current mirror to produce a current feedback signal, wherein the current mirror provides a feedback path through the current feedback signal to improve symmetry between positive and negative slewing current at the output signal; a first transistor coupled to a first input voltage to form a first input signal; a second transistor coupled to the first input signal and coupled to a second input voltage, the second input voltage being a complement of the first input voltage; a first bias circuit being coupled to the second transistor and being coupled to a bias voltage; and a second bias circuit being coupled to the bias voltage, and being coupled to the current feedback signal through at least one transistor. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30)
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31. A gain boost buffer circuit for providing gain boost of an output signal, the gain boost buffer circuit comprising:
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an output node connected to the gain boost buffer circuit that drives an output signal to the output node, wherein the gain boost buffer circuit comprises; a current mirror connected to a first supply node, the current mirror to produce a current feedback signal, wherein the current mirror provides a feedback path through the current feedback signal to improve symmetry between positive and negative slewing current at the output signal; a first transistor coupled to a first input voltage to form a first input signal; a second transistor coupled to the first input signal and coupled to a second input voltage, the second input voltage being a complement of the first input voltage; a first bias circuit being coupled to the second transistor and being coupled to a bias voltage; and a second bias circuit being coupled to the bias voltage, and being coupled to the current feedback signal through at least one transistor. - View Dependent Claims (32, 33, 34, 35, 36, 37, 38, 39, 40)
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Specification