LIQUID CRYSTAL DISPLAY AND METHOD FOR MANUFACTURING THE SAME

• US 20170212379A1
• Filed: 01/10/2017
• Published: 07/27/2017
• Est. Priority Date: 01/25/2016
• Status: Active Grant

• Current Assignee: Trivale Technologies, LLC (Vector Capital Corporation)
• Original Assignee: Mitsubishi Electric Corporation
• Inventors: GOTO, Fumihiro, MIYAKAWA, Osamu
• Granted Patent: US 9,897,866 B2
• Time in Patent Office: Days
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/133357 Planarisation layers
• CPC Class Codes: G02F 1/13394 spacers regularly patterned on the cell subtrate, e.g. walls, pillars G02F1/133377 takes precedence
• CPC Class Codes: G02F 1/13396 Spacers having different sizes
• CPC Class Codes: G02F 1/134309 characterised by their geometrical arrangement
• CPC Class Codes: G02F 1/134318 having a patterned common electrode
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/13606 having means for reducing parasitic capacitance
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/13629 Multilayer wirings
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/121 common or background
• CPC Class Codes: G02F 2201/123 pixel

Abstract

A liquid crystal display includes a first insulation substrate and a second insulation substrate on which a first pixel, a second pixel, and a third pixel are located. In the first pixel, no columnar spacer equivalent to a first columnar spacer or the second columnar spacer is provided. In the second pixel, a second interlayer insulation film has no contact hole below the first columnar spacer. In the third pixel, no common wire is provided and a third interlayer insulation film has no contact hole below the second columnar spacer.

Claims

1. A liquid crystal display comprising:

a liquid crystal layer; and

a first insulation substrate and a second insulation substrate that sandwich said liquid crystal layer and include a first pixel, a second pixel, and a third pixel located thereon,

each of said first pixel, said second pixel, and said third pixel including;

one of a plurality of signal lines and one of a plurality of scanning lines, said plurality of signal lines and said plurality of scanning lines being arranged in matrix on said first insulation substrate;

a thin film transistor that is located at an intersection of said signal line and said scanning line and is electrically connected to said signal line and said scanning line;

a planarization film having insulation properties located on said thin film transistor; and

a pixel electrode that is located on said planarization film and is electrically connected to said thin film transistor through a contact hole of said planarization film,

wherein

said first pixel includes;

a first common wire that is located on said planarization film and overlaps said scanning line in a plan view;

a first interlayer insulation film located on said pixel electrode and said first common wire; and

a first common electrode located on said first interlayer insulation film and is electrically connected to said first common wire through a contact hole of said first interlayer insulation film,

said second pixel includes;

a second common wire that is located on said planarization film and overlaps said scanning line in a plan view;

a second interlayer insulation film located on said pixel electrode and said second common wire;

a second common electrode located on said second interlayer insulation film; and

a first columnar spacer that is located above at least one of said thin film transistor, said signal line, and said scanning line and is connected to at least one of said second common electrode and said second insulation substrate,

said second interlayer insulation film has no contact hole below said first columnar spacer,

said third pixel includes;

a third interlayer insulation film located on said pixel electrode;

a third common electrode located on said third interlayer insulation film; and

a second columnar spacer that is located above at least one of said thin film transistor, said signal line, and said scanning line and is connected to said third common electrode or said second insulation substrate,

said third pixel includes no common wire equivalent to said first common wire or said second common wire below said second columnar spacer,

said third interlayer insulation film has no contact hole below said second columnar spacer, and

said first pixel includes no columnar spacer equivalent to said first columnar spacer or said second columnar spacer.

2. The liquid crystal display according to claim 1,

wherein each of said first and second common wires has a laminated structure including:

a transparent conductive film that lies directly on said planarization film; and

a conductive film that lies directly on said transparent conductive film.

3. The liquid crystal display according to claim 2,

wherein said transparent conductive film and said pixel electrode are formed of one transparent conductive film.

4. The liquid crystal display according to claim 1,

wherein proportions of said first to third pixels to a display area defined on said first and second insulation substrates are expressed by

X+Y+Z=100, 24≦

X≦

45, 1≦

Y≦

22, 54≦

Z≦

75,

where

X represents a percentage of said first pixel,

Y represents a percentage of said second pixel, and

Z represents a percentage of said third pixel.

5. The liquid crystal display according to claim 1,

wherein a height of said first columnar spacer is equal to a height of said second columnar spacer.

6. A method for manufacturing a liquid crystal display including a first insulation substrate and a second insulation substrate that sandwich a liquid crystal layer, said method comprising:

a first forming step of forming a first structure, a second structure, and a third structure;

said first forming step including

(a) forming a plurality of signal lines and a plurality of scanning lines arranged in matrix on said first insulation substrate,

(b) forming a thin film transistor at an intersection of one of said plurality of signal lines and one of said plurality of scanning line so as to electrically connect said thin film transistor to said signal line and said scanning line,

(c) forming a planarization film having insulation properties on said thin film transistor, and

(d) forming a pixel electrode on said planarization film so as to electrically connect said pixel electrode to said thin film transistor through a contact hole of said planarization film,

a second forming step of forming a first pixel from said first structure;

said second forming step including

(e-1) forming a first common wire on said planarization film in such a manner that said first common wire overlaps said scanning line in a plan view,

(f-1) forming a first interlayer insulation film on said pixel electrode and said first common wire, and

(g-1) forming a first common electrode on said first interlayer insulation film so as to electrically connect said first common electrode to said first common wire through a contact hole of said first interlayer insulation film,

a third forming step of forming a second pixel from said second structure; and

said third forming step including

(e-2) forming a second common wire on said planarization film in such a manner that said second common wire overlaps said scanning line in a plan view,

(f-2) forming a second interlayer insulation film on said pixel electrode and said second common wire,

(g-2) forming a second common electrode on said second interlayer insulation film, and

(h-2) forming a first columnar spacer above at least one of said thin film transistor, said signal line, and said scanning line so as to connect said first columnar spacer to at least one of said second common electrode and said second insulation substrate,

a fourth forming step of forming a third pixel from said third structure,

said fourth forming step including

(e-3) forming a third interlayer insulation film on said pixel electrode,

(f-3) forming a third common electrode on said third interlayer insulation film, and

(g-3) forming a second columnar spacer above at least one of said thin film transistor, said signal line, and said scanning line so as to connect said second columnar spacer to said third common electrode or said second insulation substrate,

wherein

in said first pixel, no columnar spacer equivalent to said first columnar spacer or said second columnar spacer is provided,

in said second pixel, said second interlayer insulation film has no contact hole below said first columnar spacer, and

in said third pixel, no common wire equivalent to said first common wire or said second common wire is located below said second columnar spacer and said third interlayer insulation film has no contact hole below said second columnar spacer.

7. The method for manufacturing a liquid crystal display according to claim 6,

wherein each of said first and second common wires is formed so as to have a laminated structure including:

a transparent conductive film that lies directly on said planarization film; and

a conductive film that lies directly on said transparent conductive film.

8. The method for manufacturing a liquid crystal display according to claim 7,

wherein said transparent conductive film and said pixel electrode are formed of one transparent conductive film.

9. The method for manufacturing a liquid crystal display panel according to claim 6,

wherein proportions of said first to third pixels to a display area defined on said first and second insulation substrates are expressed by

X+Y+Z=100, 24≦

X≦

45, 1≦

Y≦

22, 54≦

Z≦

75,

where

X represents a percentage of said first pixel,

Y represents a percentage of said second pixel, and

Z represents a percentage of said third pixel.

10. The method for manufacturing a liquid crystal display according to claim 6,

wherein a height of said first columnar spacer is equal to a height of said second columnar spacer.