LIQUID CRYSTAL DISPLAY PANEL

• US 20170212380A1
• Filed: 08/20/2015
• Published: 07/27/2017
• Est. Priority Date: 08/11/2015
• Status: Active Grant

• Current Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Original Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Inventors: Du, Peng
• Granted Patent: US 9,958,743 B2
• Time in Patent Office: Days
• CPC Class Codes: G02F 1/134309 characterised by their geometrical arrangement
• CPC Class Codes: G02F 1/134345 Subdivided pixels, e.g. for grey scale or redundancy
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/13624 having more than one switching element per pixel
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/121 common or background
• CPC Class Codes: G02F 2201/40 Arrangements for improving the aperture ratio

Abstract

The present invention provides a liquid crystal display panel, comprising: a control terminal of the first main thin film transistor on the nth row of the pixels connected to a branch of the scanning lines to which the nth row of the pixels correspond; the control terminal of the second main thin film transistor on the nth row of the pixels connected to a first branch of the scanning line of the (n+1)th row; the control terminal of the auxiliary thin film transistor on the (n+1)th row of pixels connected to a branch of the scanning lines of the (n+1)th row.

Claims

1. A liquid crystal display panel, comprising:

a plurality of data lines for inputting data signals;

a plurality of scanning lines for inputting scanning signals;

the scanning lines comprising a first branch and a second branch;

the first branch located on an upper edge of a pixel, the second branch located on a lower edge of the pixel; and

the first branch and the second branch respectively correspond to a position at a junction of the two adjacent pixels;

a plurality of pixels formed and enclosed by the data lines and the scanning lines, the pixels comprising main pixels and sub-pixels, the main pixels and the sub-pixels being disposed adjacently;

the main pixels being correspondingly disposed with a first main thin film transistor, a second main thin film transistor, and a first capacitor;

a control terminal of the first main thin film transistor on the nth row of the pixels connected to a branch of the scanning lines to which the nth row of the pixels correspond;

the control terminal of the second main thin film transistor on the nth row of the pixels being connected to the first branch of the scanning line to which the (n+1)th row of the pixels correspond;

the control terminal of the auxiliary thin film transistor on the (n+1)th row of pixels being connected to a branch of the scanning line to which the (n+1)th row of the pixels correspond;

an input terminal of the first main thin film transistor connected to the data line, an output terminal of the first main thin film transistor connected to the first capacitor;

the output terminal of the first main thin film transistor being further connected to the input terminal of the second main thin film transistor;

wherein n is an integer greater than or equal to 2;

the sub-pixel being correspondingly disposed with a first auxiliary thin film transistor and a second auxiliary thin film transistor; and

the input terminal of the first auxiliary thin film transistor being connected to the data line, the output terminal of the first auxiliary thin film transistor being connected to a second capacitor;

the output terminal of the first auxiliary thin film transistor being further connected to the input terminal of the second auxiliary thin film transistor;

a second control terminal of the auxiliary thin film transistor on the (n+1)th row of pixels connected to a second branch of the scanning line to which the nth row of the pixels correspond.

2. The liquid crystal display panel according to claim 1, wherein the control terminal of the first main thin film transistor on the nth row of the pixels is connected to the first branch of the scanning line to which the nth row of the pixels correspond;

the first the control terminal of auxiliary thin film transistor of the pixel adjacent to the pixel on the nth row is connected to the second branch of the scanning line to which the nth row of the pixels correspond;

the control terminal of the second main thin film transistor on the nth row of the pixels is connected to the first branch of the scanning line to which the (n+1)th row of the pixels correspond;

the second the control terminal of auxiliary thin film transistor of the pixel adjacent to the pixel on the nth row is connected to the second branch of the scanning line to which the (n−

1)th row of pixels correspond; and

the first the control terminal of auxiliary thin film transistor on the (n+1)th row of pixels is connected to the second branch of the scanning line to which the (n+1)th row of pixels correspond;

the control terminal of the first main thin film transistor of the pixel adjacent to the pixel on the (n+1)th row is connected to the first branch of the scanning line to which the (n+1)th row of pixels correspond.

3. The liquid crystal display panel according to claim 1, wherein the control terminal of the first main thin film transistor on the nth row of the pixels is connected to the second branch of the scanning line to which the nth row of the pixels correspond;

the first the control terminal of auxiliary thin film transistor of the pixel adjacent to the pixel on the nth row is connected to the first branch of the scanning line to which the nth row of the pixels correspond;

the control terminal of the second main thin film transistor on the nth row of the pixels is connected to the first branch of the scanning line to which the (n+1)th row of the pixels correspond;

the second the control terminal of auxiliary thin film transistor of the pixel adjacent to the pixel on the nth row is connected to the second branch of the scanning line to which the (n−

1)th row of pixels correspond; and

the first the control terminal of auxiliary thin film transistor on the (n+1)th row of pixels is connected to the first branch of the scanning line to which the (n+1)th row of pixels correspond;

the control terminal of the first main thin film transistor of the pixel adjacent to the pixel on the (n+1)th row is connected to the second branch of the scanning line to which the (n+1)th row of pixels correspond.

4. The liquid crystal display panel according to claim 1, wherein the main pixel is further disposed with a third capacitor;

the sub-pixel is further disposed with a fourth capacitor;

the output terminal of the second main thin film transistor is connected to the third capacitor;

the output terminal of the second auxiliary thin film transistor is connected to the fourth capacitor.

5. The liquid crystal display panel according to claim 1, wherein the liquid crystal display panel comprises a common electrode, the output terminal of the second main thin film transistor is connected to the common electrode, the output terminal of the second auxiliary thin film transistor is also connected to the common electrode.

6. The liquid crystal display panel according to claim 1, wherein when the liquid crystal display panel scans from top to bottom, a display brightness of the main pixel is less than the display brightness of the sub-pixel;

when the liquid crystal display panel scans from bottom to top, the display brightness of the main pixel is greater than or equal to the display brightness of the sub-pixel.

7. A liquid crystal display panel, comprising:

a plurality of data lines for inputting data signals;

a plurality of scanning lines for inputting scanning signals;

the scanning lines comprising a first branch and a second branch;

the first branch being located on an upper edge of a pixel, the second branch being located on a lower edge of the pixel;

a plurality of pixels formed and enclosed by the data lines and the scanning lines, the pixels comprising main pixels and sub-pixels, the main pixels and the sub-pixels being disposed adjacently;

the main pixels being correspondingly disposed with a first main thin film transistor, a second main thin film transistor, and a first capacitor;

the sub-pixels being correspondingly disposed with at least an auxiliary thin film transistor, and a second capacitor;

a control terminal of the first main thin film transistor on the nth row of the pixels connected to a branch of the scanning lines to which the nth row of the pixels correspond;

the control terminal of the second main thin film transistor on the nth row of the pixels being connected to the first branch of the scanning line to which the (n+1)th row of the pixels correspond;

the control terminal of the auxiliary thin film transistor on the (n+1)th row of pixels being connected to a branch of the scanning line to which the (n+1)th row of the pixels correspond;

an input terminal of the first main thin film transistor connected to the data line, an output terminal of the first main thin film transistor connected to the first capacitor;

the output terminal of the first main thin film transistor being further connected to the input terminal of the second main thin film transistor; and

the input terminal of the auxiliary thin film transistor being connected to the data line, the output terminal of the auxiliary thin film transistor being connected to the second capacitor, wherein n is an integer greater than or equal to 2.

8. The liquid crystal display panel according to claim 7, wherein

the sub-pixel is correspondingly disposed with a first auxiliary thin film transistor and a second auxiliary thin film transistor;

the input terminal of the first auxiliary thin film transistor is connected to the data line, the output terminal of the first auxiliary thin film transistor is connected to the second capacitor;

a second control terminal of the auxiliary thin film transistor on the (n+1)th row of pixels is connected to a second branch of the scanning line to which the nth row of the pixels correspond.

9. The liquid crystal display panel according to claim 8, wherein the control terminal of the first main thin film transistor on the nth row of the pixels is connected to the first branch of the scanning line to which the nth row of the pixels correspond;

the first the control terminal of the auxiliary thin film transistor of the pixel adjacent to the pixel on the nth row is connected to the second branch of the scanning line to which the nth row of the pixels correspond;

the control terminal of the second main thin film transistor on the nth row of the pixels is connected to the first branch of the scanning line to which the (n+1)th row of the pixels correspond;

the second control terminal of the auxiliary thin film transistor of the pixel adjacent to the pixel on the nth row is connected to the second branch of the scanning line to which the (n−

1)th row of pixels correspond; and

the first the control terminal of auxiliary thin film transistor on the (n+1)th row of pixels is connected to the second branch of the scanning line to which the (n+1)th row of pixels correspond;

the control terminal of the first main thin film transistor of the pixel adjacent to the pixel on the (n+1)th row is connected to the first branch of the scanning line to which the (n+1)th row of pixels correspond.

10. The liquid crystal display panel according to claim 8, wherein the control terminal of the first main thin film transistor on the nth row of the pixels is connected to the second branch of the scanning line to which the nth row of the pixels correspond;

the first the control terminal of the auxiliary thin film transistor of the pixel adjacent to the pixel on the nth row is connected to the first branch of the scanning line to which the nth row of the pixels correspond;

the control terminal of the second main thin film transistor on the nth row of the pixels is connected to the first branch of the scanning line to which the (n+1)th row of the pixels correspond;

the second the control terminal of the auxiliary thin film transistor of the pixel adjacent to the pixel on the nth row is connected to the second branch of the scanning line to which the (n−

1)th row of pixels correspond; and

the first the control terminal of auxiliary thin film transistor on the (n+1)th row of pixels is connected to the first branch of the scanning line to which the (n+1)th row of pixels correspond;

the control terminal of the first main thin film transistor of the pixel adjacent to the pixel on the (n+1)th row is connected to the second branch of the scanning line to which the (n+1)th row of pixels correspond.

11. The liquid crystal display panel according to claim 8, wherein the main pixel is further disposed with a third capacitor;

the sub-pixel is further disposed with a fourth capacitor;

the output terminal of the second main thin film transistor is connected to the third capacitor;

the output terminal of the second auxiliary thin film transistor is connected to the fourth capacitor.

12. The liquid crystal display panel according to claim 8, wherein the liquid crystal display panel comprises a common electrode, the output terminal of the second main thin film transistor is connected to the common electrode, the output terminal of the second auxiliary thin film transistor is also connected to the common electrode.

13. The liquid crystal display panel according to claim 7, wherein the sub-pixel is correspondingly disposed with only one auxiliary thin film transistor;

the control terminal of the first main thin film transistor on the nth row of the pixels is connected to the second branch of the scanning line to which the nth row of the pixels correspond;

the control terminal of the auxiliary thin film transistor of the pixel adjacent to the pixel on the nth row is connected to the first branch of the scanning line to which the nth row of the pixels correspond;

the control terminal of the second main thin film transistor on the nth row of the pixels is connected to the first branch of the scanning line to which the (n+1)th row of the pixels correspond; and

the control terminal of auxiliary thin film transistor on the (n+1)th row of pixels is connected to the first branch of the scanning line to which the (n+1)th row of pixels correspond;

the control terminal of the first main thin film transistor of the pixel adjacent to the pixel on the (n+1)th row is connected to the second branch of the scanning line to which the (n+1)th row of pixels correspond.

14. The liquid crystal display panel according to claim 13, wherein the liquid crystal display panel comprises a common electrode, the main pixel is further disposed with a third capacitor;

the output terminal of the second main thin film transistor is connected to the third capacitor or the common electrode.

15. The liquid crystal display panel according to claim 7, wherein the first branch and the second branch respectively correspond to a position at a junction of the two adjacent pixels.

16. The liquid crystal display panel according to claim 7, wherein when the liquid crystal display panel scans from top to bottom, a display brightness of the main pixel is less than the display brightness of the sub-pixel;

when the liquid crystal display panel scan from bottom to top, the display brightness of the main pixel is greater than or equal to the display brightness of the sub-pixel.