Reducing Read Access Latency by Straddling Pages Across Non-Volatile Memory Channels

• US 20170212692A1
• Filed: 01/25/2016
• Published: 07/27/2017
• Est. Priority Date: 01/25/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Camp, Charles J., Fisher, Timothy J., Fry, Aaron D., Ioannou, Nikolas, Parnell, Thomas, Pletka, Roman, Tomic, Sasa
• Granted Patent: US 9,940,034 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/152 Virtualized environment, e.g. logically partitioned system
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/0664 at device level, e.g. emulation of a storage device or system
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

A mechanism is provided in a non-volatile memory controller for reducing read access latency by straddling pages across non-volatile memory channels. Responsive to a request to write a logical page to a non-volatile memory array, the non-volatile memory controller determines whether the logical page fits into a current physical page. Responsive to determining the logical page does not fit into the current physical page, the non-volatile memory controller writes a first portion of the logical page to a first physical page in a first block and writes a second portion of the logical page to a second physical page in a second block. The first physical page and the second physical page are on different non-volatile memory channels.

Claims

1. A method, in a non-volatile memory controller, for reducing read access latency by straddling pages across non-volatile memory channels, the method comprising:

responsive to a request to write a logical page to a non-volatile memory array, determining whether the logical page fits into a current physical page; and

responsive to determining the logical page does not fit into the current physical page, writing a first portion of the logical page to a first physical page in a first block and writing a second portion of the logical page to a second physical page in a second block, wherein the first physical page and the second physical page are on different non-volatile memory channels.

2. The method of claim 1, wherein the first physical page and the second physical page are in a same physical page stripe.

3. The method of claim 1, further comprising:

responsive to determining the logical page does not fit into the current physical page and writing the first portion of the logical page to the first physical page and writing the second portion of the logical page to the second physical page, setting a straddle bit in a logical page table entry corresponding to the logical page.

4. The method of claim 1, further comprising:

responsive to receiving from a user a request to read the logical page from the non-volatile memory array and responsive to determining that the logical page straddles non-volatile memory channels, issuing parallel reads over two non-volatile memory channels to read the first physical page and the second physical page.

5. The method of claim 4, further comprising:

responsive to reading the first physical page and the second physical page, extracting the first portion of the logical page from the first physical page and the second portion of the logical page from the second physical page, coalescing the first portion of the logical page and the second portion of the logical page to form the logical page, and returning the logical page to the user.

6. The method of claim 4, further comprising:

checking an entry in a logical page table to determine whether a straddle bit is set for the logical page; and

determining that the logical page straddles non-volatile memory channels responsive to the straddle bit being set for the logical page.

7. The method of claim 4, wherein issuing parallel reads over two non-volatile memory channels comprises consulting an additional table to obtain a location of the second physical page and reading from a physical page stripe in which the first physical page and the second physical page are stored.

8. A computer program product comprising a computer readable storage medium having a computer readable program stored therein, wherein the computer readable program, when executed on a non-volatile memory controller, causes the non-volatile memory controller to:

responsive to a request to write a logical page to a non-volatile memory array, determine whether the logical page fits into a current physical page; and

responsive to determining the logical page does not fit into the current physical page, write a first portion of the logical page to a first physical page in a first block and write a second portion of the logical page to a second physical page in a second block, wherein the first physical page and the second physical page are on different non-volatile memory channels.

9. The computer program product of claim 8, wherein the first physical page and the second physical page are in a same physical page stripe.

10. The computer program product of claim 8, wherein the computer readable program further causes the non-volatile memory controller to:

responsive to determining the logical page does not fit into the current physical page and writing the first portion of the logical page to the first physical page and writing the second portion of the logical page to the second physical page, set a straddle bit in a logical page table entry corresponding to the logical page.

11. The computer program product of claim 8, wherein the computer readable program further causes the non-volatile memory controller to:

responsive to receiving from a user a request to read the logical page from the non-volatile memory array and responsive to determining that the logical page straddles non-volatile memory channels, issue parallel reads over two non-volatile memory channels to read the first physical page and the second physical page.

12. The computer program product of claim 11, wherein the computer readable program further causes the non-volatile memory controller to:

responsive to reading the first physical page and the second physical page, extract the first portion of the logical page from the first physical page and the second portion of the logical page from the second physical page, coalesce the first portion of the logical page and the second portion of the logical page to form the logical page, and return the logical page to the user.

13. The computer program product of claim 11, wherein the computer readable program further causes the non-volatile memory controller to:

check an entry in a logical page table to determine whether a straddle bit is set for the logical page; and

determine that the logical page straddles non-volatile memory channels responsive to the straddle bit being set for the logical page.

14. The computer program product of claim 11, wherein issuing parallel reads over two non-volatile memory channels comprises consulting an additional table to obtain a location of the second physical page and reading from a physical page stripe in which the first physical page and the second physical page are stored.

15. A storage device comprising:

a non-volatile memory array;

a non-volatile memory controller; and

a memory coupled to the non-volatile memory controller, wherein the memory comprises instructions which, when executed by the non-volatile memory controller, cause the non-volatile memory controller to;

responsive to a request to write a logical page to a non-volatile memory array, determine whether the logical page fits into a current physical page; and

responsive to determining the logical page does not fit into the current physical page, write a first portion of the logical page to a first physical page in a first block and write a second portion of the logical page to a second physical page in a second block, wherein the first physical page and the second physical page are on different non-volatile memory channels.

16. The storage device of claim 15, wherein the first physical page and the second physical page are in a same physical page stripe.

17. The storage device of claim 15, wherein the instructions further cause the non-volatile memory controller to:

responsive to determining the logical page does not fit into the current physical page and writing the first portion of the logical page to the first physical page and writing the second portion of the logical page to the second physical page, set a straddle bit in a logical page table entry corresponding to the logical page.

18. The storage device of claim 15, wherein the instructions further cause the non-volatile memory controller to:

responsive to receiving from a user a request to read the logical page from the non-volatile memory array and responsive to determining that the logical page straddles non-volatile memory channels, consult an additional table to obtain a location of the second physical page and issue parallel reads over two non-volatile memory channels to read the first physical page and the second physical page.

19. The storage device of claim 18, wherein the instructions further cause the non-volatile memory controller to:

responsive to reading the first physical page and the second physical page, extract the first portion of the logical page from the first physical page and the second portion of the logical page from the second physical page, coalesce the first portion of the logical page and the second portion of the logical page to form the logical page, and return the logical page to the user.

20. The storage device of claim 18, wherein the instructions further cause the non-volatile memory controller to:

check an entry in a logical page table to determine whether a straddle bit is set for the logical page; and

determine that the logical page straddles non-volatile memory channels responsive to the straddle bit being set for the logical page.