LOW POWER VLSI DESIGNS USING CIRCUIT FAILURE IN SEQUENTIAL CELLS AS LOW VOLTAGE CHECK FOR LIMIT OF OPERATION
First Claim
1. A method for reducing the voltage at which a design of a digital electronic device is operated, comprising:
- providing a design for a digital electronic device;
determining the lowest voltage Vmin at which the design will operate correctly by operating the design at successively lower voltages until a point of failure is reached; and
operating the design at Vmin.
3 Assignments
0 Petitions
Accused Products
Abstract
Low power VLSI designs using circuit failure in sequential cells as low voltage check for limit of operation of the design are provided. One such method involves the addition of a plurality of bits for sequential elements in the design including set of flip-flops, RAMs, ROMs and register files to add parity or single error correct and double error detect mechanism, a method to detect the parity errors or a single or double bit error in the sequential elements, starting at a nominal voltage of operation and gradually lowering the voltage setting till the first error is detected in the sequential elements, increasing the operating voltage by predetermined step above the voltage of first fail to achieve the optimal lowest voltage of correct operation of the design, storing this optimal voltage setting in a non-volatile memory for subsequent use.
10 Citations
28 Claims
-
1. A method for reducing the voltage at which a design of a digital electronic device is operated, comprising:
-
providing a design for a digital electronic device; determining the lowest voltage Vmin at which the design will operate correctly by operating the design at successively lower voltages until a point of failure is reached; and
operating the design at Vmin. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
-
-
15. The method of claim 1, wherein the digital electronic device is a VLSI device. 16-26. (canceled)
-
27. A method for detecting errors in a plurality of flip-flops in a VLSI design, comprising:
-
grouping the plurality of flip-flops into sets of flip-flops; and for each set of flip-flops, (a) XORing the inputs of member flip-flops of the set to create a first signal, (b) XORing the outputs of member flip-flops of the set to create a second signal, (c) inputting the first signal into a parity flip-flop associated with the set of flip-flops, (d) comparing the first and second signals, and (e) outputting an error signal if the first and second signals do not match.
-
-
28. A method for detecting errors in a plurality of flip-flops in a VLSI design containing flip-flops, 1-bit memory devices and 2-bit memory devices, the method comprising:
-
receiving first, second and third sets of error signals corresponding, respectively, to the flip-flops, 1-bit memory devices and 2-bit memory devices; ORing the first set of error signals to generate a first check signal; ORing the second set of error signals to generate a second check signal; ORing the third set of error signals to generate a third check signal; inputting the first, second and third check signals into first, second and third parity flip-flops, respectively; comparing the output signal of the first parity flip-flop to the first check signal, and generating an error code indicating an error in the flip-flops if the two signals do not match; comparing the output signal of the second parity flip-flop to the second check signal, and generating an error code indicating an error in the 1-bit memory devices if the two signals do not match; and comparing the output signal of the third parity flip-flop to the third check signal, and generating an error code indicating an error in the 2-bit memory devices if the two signals do not match.
-
Specification