LOW POWER VLSI DESIGNS USING CIRCUIT FAILURE IN SEQUENTIAL CELLS AS LOW VOLTAGE CHECK FOR LIMIT OF OPERATION

• US 20170212972A1
• Filed: 10/07/2016
• Published: 07/27/2017
• Est. Priority Date: 08/07/2015
• Status: Active Grant

• Current Assignee: Siemens Industry Software Limited (Siemens AG)
• Original Assignee: Austemper Design Systems Inc. (Siemens AG)
• Inventors: Pillay, Sanjay
• Granted Patent: US 10,522,237 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 2117/02 Fault tolerance, e.g. for transient fault suppression
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 2029/5004 Voltage
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/08 Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
• CPC Class Codes: G11C 29/12015 comprising clock generation or timing circuitry
• CPC Class Codes: G11C 29/22 Accessing serial memories
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 29/54 Arrangements for designing test circuits, e.g. design for test [DFT] tools
• CPC Class Codes: G11C 7/1063 Control signal output circuits, e.g. status or busy flags, feedback command signals
• CPC Class Codes: H03K 19/0008 Arrangements for reducing power consumption
• CPC Class Codes: H03K 19/21 EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical

Abstract

Low power VLSI designs using circuit failure in sequential cells as low voltage check for limit of operation of the design are provided. One such method involves the addition of a plurality of bits for sequential elements in the design including set of flip-flops, RAMs, ROMs and register files to add parity or single error correct and double error detect mechanism, a method to detect the parity errors or a single or double bit error in the sequential elements, starting at a nominal voltage of operation and gradually lowering the voltage setting till the first error is detected in the sequential elements, increasing the operating voltage by predetermined step above the voltage of first fail to achieve the optimal lowest voltage of correct operation of the design, storing this optimal voltage setting in a non-volatile memory for subsequent use.

Claims

1. A method for reducing the voltage at which a design of a digital electronic device is operated, comprising:

providing a design for a digital electronic device;

determining the lowest voltage V_min at which the design will operate correctly by operating the design at successively lower voltages until a point of failure is reached; and

operating the design at V_min.

2. The method of claim 1, further comprising:

creating a circuit wrapper around sequential elements in the design, wherein said circuit wrapper adds a plurality of bits to each of the sequential elements.

3. The method of claim 2, further comprising:

detecting the correct operation of each of the plurality of sequential elements by utilizing a circuit to read the bits added to each of the sequential elements.

4. The method of claim 3, wherein the first voltage at which a point of failure is reached by operating the design at successively lower voltages is V_fail, and wherein V_min is obtained by adding a predetermined margin to V_fail.

5. The method of claim 1, wherein the voltage at which a point of failure is reached is V_fail, and further comprising:

storing V_min in a non-volatile memory.

6. The method of claim 5, further comprising:

restoring the voltage to the value of V_min stored in the non-volatile memory.

7. The method of claim 2, further comprising:

generating a parity bit for each of the input bits of the sequential elements in the design through the use of the circuit wrapper, wherein each of the sequential elements is selected from the group consisting of flip-flops, RAMs, ROMs and register files, and wherein each of the parity bits has the value of either even or odd parity.

8. The circuit of claim 2, further comprising:

generating single error correct and double error detect code words (SECDED) for sequential elements in the design, wherein each of said sequential elements is selected from the group consisting of flip-flops, RAMs, ROMs and register files.

9. The method of claim 7, further comprising:

checking the output of each of the sequential elements in the design for correctness based the associated parity bit.

10. The method of claim 8, further comprising:

checking the output of each sequential element in the design for correctness based on the associated SECDED.

11. The method of claim 9, wherein determining V_min includes:

iteratively lowering the voltage based on the correctness of the output of the sequential elements.

12. The method of claim 10, wherein determining V_min includes:

iteratively lowering the voltage based on the correctness of the output of the sequential elements.

13. The method of claim 11, further comprising:

increasing the voltage by a predetermined step once the first failure is detected based on the correctness of the output of the sequential elements.

14. The method of claim 12, further comprising:

increasing the voltage by a predetermined step once the first failure is detected based on the correctness of the output of the sequential elements.

15. The method of claim 1, wherein the digital electronic device is a VLSI device. 16-26. (canceled)

27. A method for detecting errors in a plurality of flip-flops in a VLSI design, comprising:

grouping the plurality of flip-flops into sets of flip-flops; and

for each set of flip-flops,

(a) XORing the inputs of member flip-flops of the set to create a first signal,

(b) XORing the outputs of member flip-flops of the set to create a second signal,

(c) inputting the first signal into a parity flip-flop associated with the set of flip-flops,

(d) comparing the first and second signals, and

(e) outputting an error signal if the first and second signals do not match.

28. A method for detecting errors in a plurality of flip-flops in a VLSI design containing flip-flops, 1-bit memory devices and 2-bit memory devices, the method comprising:

receiving first, second and third sets of error signals corresponding, respectively, to the flip-flops, 1-bit memory devices and 2-bit memory devices;

ORing the first set of error signals to generate a first check signal;

ORing the second set of error signals to generate a second check signal;

ORing the third set of error signals to generate a third check signal;

inputting the first, second and third check signals into first, second and third parity flip-flops, respectively;

comparing the output signal of the first parity flip-flop to the first check signal, and generating an error code indicating an error in the flip-flops if the two signals do not match;

comparing the output signal of the second parity flip-flop to the second check signal, and generating an error code indicating an error in the 1-bit memory devices if the two signals do not match; and

comparing the output signal of the third parity flip-flop to the third check signal, and generating an error code indicating an error in the 2-bit memory devices if the two signals do not match.