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FIRMWARE SECURITY INTERFACE FOR FIELD PROGRAMMABLE GATE ARRAYS

  • US 20170213053A1
  • Filed: 01/25/2016
  • Published: 07/27/2017
  • Est. Priority Date: 01/25/2016
  • Status: Active Grant
First Claim
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1. A system for securing a field-programmable gate array, the system comprising:

  • a first machine-readable memory storing a first operating system that implements a secure environment for a field-programmable gate array (FPGA);

    a second machine-readable memory storing a second operating system that implements a non-secure environment for the FPGA;

    at least one hardware processor of the FPGA communicatively coupled to the first machine-readable memory and the second machine-readable memory, the at least one hardware processor configurable to;

    transition to the secure environment by executing the first operating system;

    reset a watchdog timer communicatively coupled to the at least one hardware processor by loading a register associated with the watchdog timer with a predetermined value; and

    transition to the non-secure environment by executing the second operating system; and

    programmable logic of the FPGA communicatively coupled to the at least one hardware processor, the programmable logic configurable to;

    instruct the at least one hardware processor to transition to the secure environment;

    retrieve an event value from a status register associated with the watchdog timer; and

    determine whether the first operating system was executed by the at least one hardware processor by comparing the retrieved event value with a second predetermined value.

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