Clock Switching in Always-On Component

• US 20170213557A1
• Filed: 04/07/2017
• Published: 07/27/2017
• Est. Priority Date: 02/12/2015
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Kosut, Alexei E., Gulati, Manu, Herbeck, Gilbert H., Jones, Girault W., Millet, Timothy J.
• Granted Patent: US 9,928,838 B2
• Time in Patent Office: Days
• CPC Class Codes: G10L 15/08 Speech classification or search
• CPC Class Codes: G10L 15/22 Procedures used during a speech recognition process, e.g. man-machine dialogue
• CPC Class Codes: G10L 15/28 Constructional details of speech recognition systems
• CPC Class Codes: G10L 2015/088 Word spotting
• CPC Class Codes: G10L 2015/223 Execution procedure of a spoken command

Abstract

In an embodiment, a system on a chip (SOC) may include one or more central processing units (CPUs), a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples and match those audio samples against a predetermined pattern. The circuit may operate according to a first clock during the time that the rest of the SOC is powered down. In response to detecting the predetermined pattern in the samples, the circuit may cause the memory controller and processors to power up. During the power up process, a second clock having one or more better characteristics than the first clock may become available. The circuit may switch to the second clock while preserving the samples, or losing at most one sample, or no more than a threshold number of samples.

Claims

1. An integrated circuit comprising:

one or more processors; and

a first circuit coupled to the one or more processors, wherein the first circuit, during use;

remains powered up during a time that the one or more processors are powered down;

receives a first plurality of audio samples captured by one or more audio input devices during the time that the one or more processors are powered down, wherein the first circuit operates according to a first clock during the time that the one or more processors are powered down;

detects a predetermined pattern in the first plurality of audio samples;

causes the one or more processors to power up responsive to detecting the predetermined pattern, wherein a second clock activates responsive to the power up; and

switches to the second clock responsive to the second clock becoming operable, wherein the switch is performed when both the first clock and the second clock are in a low phase to reduce a probability of losing an audio sample.

2. The integrated circuit as recited in claim 1 wherein at least one characteristic of the second clock is nearer to an ideal clock characteristic than a corresponding characteristic of the first clock.

3. The integrated circuit as recited in claim 2 wherein the ideal clock characteristic is a lack of phase noise.

4. The integrated circuit as recited in claim 2 wherein the ideal clock characteristic is about a 50% duty cycle.

5. The integrated circuit as recited in claim 2 wherein the ideal clock characteristic is a lack of period jitter.

6. The integrated circuit as recited in claim 2 wherein the ideal clock characteristic is frequency accuracy.

7. The integrated circuit as recited in claim 1 wherein the probability is reduced to zero.

8. The integrated circuit as recited in claim 1 wherein the predetermined pattern represents sound comprising a verbal utterance of one or more words.

9. The integrated circuit as recited in claim 1 further comprising a memory controller coupled to the first circuit, wherein the first circuit, during use, provides one or more memory controller parameters to the memory controller to program the memory controller for operation responsive to the power up.

10. The integrated circuit as recited in claim 1 wherein the first circuit comprises a buffer to store the first plurality of the audio samples and a second plurality of audio samples received during and after the power up, wherein at least one of the second plurality of audio samples are captured responsive to the second clock, during use, and wherein the first circuit writes the first plurality of samples and the second plurality of samples to the memory during use.

11. An integrated circuit comprising:

one or more processors;

an oscillator circuit that generates a first clock during use;

a phase locked loop circuit (PLL) that generates a second clock during use; and

a first circuit coupled to the one or more processors, the oscillator circuit, and the PLL, wherein the first circuit, during use;

remains powered up during a time that the one or more processors are powered down;

receives a first plurality of audio samples captured by one or more audio input devices during the time that the one or more processors are powered down, wherein the first circuit operates according to the first clock during the time that the one or more processors are powered down;

detects a predetermined pattern in the first plurality of audio samples;

causes the one or more processors to power up responsive to detecting the predetermined pattern, wherein the PLL generates the second clock responsive to the power up; and

switches to the second clock responsive to the PLL locking for the second clock.

12. The integrated circuit as recited in claim 11 wherein the first circuit, during use, switches to the second clock during a low phase of both the first clock and the second clock.

13. The integrated circuit as recited in claim 12 wherein switching during the low phase ensures that no audio samples are lost.

14. The integrated circuit as recited in claim 11 wherein the first circuit, during use, switches to the second clock during one or more clock cycles that are separated from arrival times of audio samples.

15. The integrated circuit as recited in claim 14 wherein switching during the one or more clock cycles ensures that no audio samples are lost.

16. The integrated circuit as recited in claim 11 wherein the PLL is also a clock source to other portions of the integrated circuit.

17. An integrated circuit comprising:

one or more processors; and

a first circuit coupled to the one or more processors, wherein the first circuit, during use;

receives a first plurality of audio samples captured by one or more audio input devices during a time that the one or more processors are powered down, wherein the first circuit operates according to a first clock during the time that the one or more processors are powered down;

detects a predetermined pattern in the first plurality of audio samples;

causes the one or more processors to power up responsive to detecting the predetermined pattern, wherein a second clock activates responsive to the power up;

switches to the second clock responsive to the second clock becoming operable;

receives a second plurality of audio samples during operation with the second clock;

writes the first plurality of audio samples and the second plurality of audio samples to memory as a single phrase even though the first plurality of samples and the second plurality of samples are captured according to different clocks.

18. The integrated circuit as recited in claim 17 wherein the one or more processors process the first plurality of audio samples and the second plurality of audio samples as a single phrase.

19. The integrated circuit as recited in claim 17 wherein the single phrase is treated as a single contiguous set of audio samples.

20. The integrated circuit as recited in claim 17 wherein the first plurality of audio samples represent sound that includes one or more key words, and the second plurality of audio samples represent sound that includes one or more additional words.