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INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREOF

  • US 20170213828A1
  • Filed: 03/18/2016
  • Published: 07/27/2017
  • Est. Priority Date: 01/21/2016
  • Status: Active Grant
First Claim
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1. An integrated circuit comprising:

  • a substrate;

    at least one n-type semiconductor device present on the substrate, wherein;

    the n-type semiconductor device comprises a first semiconductor fin,the n-type semiconductor device comprises a gate structure having a bottom surface overlying the first semiconductor fin and facing the first semiconductor fin and at least one sidewall overlying the first semiconductor fin, andthe bottom surface of the gate structure of the n-type semiconductor device and the sidewall of the gate structure of the n-type semiconductor device intersect to form an interior angle; and

    at least one p-type semiconductor device present on the substrate, wherein;

    the p-type semiconductor device comprises a second semiconductor fin,the p-type semiconductor device comprises a gate structure having a bottom surface overlying the second semiconductor fin and facing the second semiconductor fin and at least one sidewall overlying the second semiconductor fin, andthe bottom surface of the gate structure of the p-type semiconductor device and the sidewall of the gate structure of the p-type semiconductor device intersect to form an interior angle smaller than the interior angle of the gate structure of the n-type semiconductor device.

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