INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREOF
First Claim
1. An integrated circuit comprising:
- a substrate;
at least one n-type semiconductor device present on the substrate, wherein;
the n-type semiconductor device comprises a first semiconductor fin,the n-type semiconductor device comprises a gate structure having a bottom surface overlying the first semiconductor fin and facing the first semiconductor fin and at least one sidewall overlying the first semiconductor fin, andthe bottom surface of the gate structure of the n-type semiconductor device and the sidewall of the gate structure of the n-type semiconductor device intersect to form an interior angle; and
at least one p-type semiconductor device present on the substrate, wherein;
the p-type semiconductor device comprises a second semiconductor fin,the p-type semiconductor device comprises a gate structure having a bottom surface overlying the second semiconductor fin and facing the second semiconductor fin and at least one sidewall overlying the second semiconductor fin, andthe bottom surface of the gate structure of the p-type semiconductor device and the sidewall of the gate structure of the p-type semiconductor device intersect to form an interior angle smaller than the interior angle of the gate structure of the n-type semiconductor device.
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Accused Products
Abstract
An integrated circuit includes a substrate, at least one n-type semiconductor device, and at least one p-type semiconductor device. The n-type semiconductor device is present on the substrate. The n-type semiconductor device includes a gate structure having a bottom surface and at least one sidewall. The bottom surface of the gate structure of the n-type semiconductor device and the sidewall of the gate structure of the n-type semiconductor device intersect to form an interior angle. The p-type semiconductor device is present on the substrate. The p-type semiconductor device includes a gate structure having a bottom surface and at least one sidewall. The bottom surface of the gate structure of the p-type semiconductor device and the sidewall of the gate structure of the p-type semiconductor device intersect to form an interior angle smaller than the interior angle of the gate structure of the n-type semiconductor device.
19 Citations
25 Claims
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1. An integrated circuit comprising:
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a substrate; at least one n-type semiconductor device present on the substrate, wherein; the n-type semiconductor device comprises a first semiconductor fin, the n-type semiconductor device comprises a gate structure having a bottom surface overlying the first semiconductor fin and facing the first semiconductor fin and at least one sidewall overlying the first semiconductor fin, and the bottom surface of the gate structure of the n-type semiconductor device and the sidewall of the gate structure of the n-type semiconductor device intersect to form an interior angle; and at least one p-type semiconductor device present on the substrate, wherein; the p-type semiconductor device comprises a second semiconductor fin, the p-type semiconductor device comprises a gate structure having a bottom surface overlying the second semiconductor fin and facing the second semiconductor fin and at least one sidewall overlying the second semiconductor fin, and the bottom surface of the gate structure of the p-type semiconductor device and the sidewall of the gate structure of the p-type semiconductor device intersect to form an interior angle smaller than the interior angle of the gate structure of the n-type semiconductor device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 21, 22, 23, 24)
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10. An integrated circuit comprising:
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a substrate; at least one n-type semiconductor device present on the substrate, wherein; the n-type semiconductor device comprises a first semiconductor fin, the n-type semiconductor device comprises a first gate structure, the first gate structure comprises a top portion overlying the first semiconductor fin and a bottom portion overlying the first semiconductor fin and present between the top portion and the first semiconductor fin, the top portion has a first top width, and the bottom portion has a first bottom width; and at least one p-type semiconductor device present on the substrate, wherein; the p-type semiconductor device comprises a second semiconductor fin the p-type semiconductor device comprises a second gate structure, the second gate structure comprises a top portion overlying the second semiconductor fin and a bottom portion overlying the second semiconductor fin and present between the top portion and the second semiconductor fin, the top portion has a second top width, the bottom portion has a second bottom width, and the first gate structure and the second gate structure substantially satisfy; (Wb2−
Wt2)>
(Wb1−
Wt1), wherein Wb1 is the first bottom width of the bottom portion of the first gate structure, Wt1 is the first top width of the top portion of the first gate structure, Wb2 is the second bottom width of the bottom portion of the second gate structure, and Wt2 is the second top width of the top portion of the second gate structure. - View Dependent Claims (11, 12, 13, 14, 15)
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16-20. -20. (canceled)
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25. An integrated circuit comprising:
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a substrate; at least one n-type semiconductor device present on the substrate, wherein; the n-type semiconductor device comprises a first semiconductor fin, the n-type semiconductor device comprises a gate structure having a sidewall that comprises a non-tapered, vertical portion overlying the first semiconductor fin and extending from a top surface of the gate structure of the n-type semiconductor device overlying the first semiconductor fin to a bottom surface of the gate structure of the n-type semiconductor device overlying the first semiconductor fin; and at least one p-type semiconductor device present on the substrate, wherein; the p-type semiconductor device comprises a second semiconductor fin, the p-type semiconductor device comprises a gate structure having a sidewall that comprises a non-tapered, vertical portion overlying the second semiconductor fin and a tapered portion overlying the second semiconductor fin, wherein; the non-tapered, vertical portion extends from a top surface of the gate structure of the p-type semiconductor device overlying the second semiconductor fin to the tapered portion, and the tapered portion extends from the non-tapered, vertical portion to a bottom surface of the gate structure of the p-type semiconductor device overlying the second semiconductor fin.
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Specification