Tuning Tensile Strain on FinFET

• US 20170213830A1
• Filed: 04/07/2017
• Published: 07/27/2017
• Est. Priority Date: 05/23/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hsu, Ting-Hung, Huang, Jiun-Jia, Lin, Zhi-Chang, Ching, Kuo-Cheng, Chen, Guan-Lin
• Granted Patent: US 10,453,842 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02356 treatment to change the morphology of the insulating layer, e.g. transformation of an amorphous layer into a crystalline layer
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A fin field effect transistor (FinFET) having a tunable tensile strain and an embodiment method of tuning tensile strain in an integrated circuit are provided. The method includes forming a source/drain region on opposing sides of a gate region in a fin, forming spacers over the fin, the spacers adjacent to the source/drain regions, depositing a dielectric between the spacers; and performing an annealing process to contract the dielectric, the dielectric contraction deforming the spacers, the spacer deformation enlarging the gate region in the fin.

Claims

1. A semiconductor device comprising:

a first device comprising;

a first fin;

first source/drain regions in the first fin on opposing sides of a first channel region;

a first gate electrode overlying the first channel region; and

a first dielectric layer on opposing sides of the first gate electrode, the first gate electrode having substantially linear sidewalls; and

a second device comprising;

a second fin;

second source/drain regions in the second fin on opposing sides of a second channel region;

a second gate electrode overlying the second channel region; and

a second dielectric layer on opposing sides of the second gate electrode, the second gate electrode having convex sidewalls projecting toward the second dielectric layer.

2. The semiconductor device of claim 1, wherein the first device is a p-type metal-oxide-semiconductor (PMOS) device, and the second device comprises an n-type metal-oxide-semiconductor (NMOS) device.

3. The semiconductor device of claim 1, further comprising a second spacer interposed between the second gate electrode and the second dielectric layer.

4. The semiconductor device of claim 3, further comprising a first spacer interposed between the first gate electrode and the first dielectric layer.

5. The semiconductor device of claim 1, wherein the second device has a longer channel than the first device.

6. The semiconductor device of claim 1, wherein the first dielectric layer comprises a different material than the second dielectric layer.

7. The semiconductor device of claim 1, wherein the second dielectric layer is more dense than the first dielectric layer.

8. A semiconductor device comprising:

a fin extending from a substrate;

source/drain regions in the fin on opposing sides of a channel region;

a gate over the channel region;

a contracted dielectric disposed over the source/drain regions; and

spacers interposed between the gate and the contracted dielectric, the spacers having a concave surface extending toward the contracted dielectric.

9. The semiconductor device of claim 8, wherein a contour of sidewalls of the contracted dielectric is equivalent to a contour of the spacers.

10. The semiconductor device of claim 8, wherein the contracted dielectric has been reduced in size about 15% to about 18% relative to an original size of the contracted dielectric.

11. The semiconductor device of claim 8, wherein the contracted dielectric is vertically aligned with the source/drain regions.

12. The semiconductor device of claim 8, further comprising an interfacial oxide and a high-k dielectric interposed between the fin and the gate.

13. The semiconductor device of claim 8, wherein the gate comprises a metal gate electrode.

14. A semiconductor device comprising:

a first device comprising;

a first fin;

first source/drain regions in the first fin on opposing sides of a first channel region;

a first gate electrode overlying the first channel region; and

a first dielectric layer on opposing sides of the first gate electrode, the first gate electrode having convex sidewalls projecting toward the first dielectric layer;

a second device comprising;

a second fin;

second source/drain regions in the second fin on opposing sides of a second channel region;

a second gate electrode overlying the second channel region, sidewalls of the second gate electrode having a different shape than sidewalls of the first gate electrode; and

a second dielectric layer on opposing sides of the second gate electrode; and

an interlayer dielectric layer over the first fin and the second fin, the interlayer dielectric layer extending along sidewalls of the first dielectric layer and the second dielectric layer.

15. The semiconductor device of claim 14, wherein the second gate electrode has linear sidewalls.

16. The semiconductor device of claim 14, wherein the first device is an NMOS device.

17. The semiconductor device of claim 14, further comprising spacers interposed between the first gate electrode and the first dielectric layer, the spacers having curved sidewalls facing the first gate electrode.

18. The semiconductor device of claim 14, wherein the first dielectric layer and the second dielectric layer are different materials.

19. The semiconductor device of claim 14, wherein the first gate electrode has a first height, the second gate electrode has a second height, the first height being different than the second height.

20. The semiconductor device of claim 14, wherein the first dielectric layer is denser than the second dielectric layer.