METHOD AND APPARATUS FOR MOS DEVICE WITH DOPED REGION

• US 20170213898A1
• Filed: 02/10/2017
• Published: 07/27/2017
• Est. Priority Date: 02/27/2014
• Status: Active Grant

• Current Assignee: Vanguard International Semiconductor Corporation
• Original Assignee: Vanguard International Semiconductor Corporation
• Inventors: Lee, Tsung-Hsiung, Lin, Shin-Cheng
• Granted Patent: US 10,644,132 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/66681 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7823 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A semiconductor device is provided. The device may include a semiconductor layer; and a doped well disposed in the semiconductor layer and having a first conductivity type. The device may also include a drain region, a source region, and a body region, where the source and body regions may operate in different voltages. Further, the device may include a first doped region having a second conductivity type, the first doped region disposed between the source region and the doped well; and a second doped region having the first conductivity type and disposed under the source region. The device may include a third doped region having the second conductivity type and disposed in the doped well; and a fourth doped region disposed above the third doped region, the fourth doped region having the first conductivity type. Additionally, the device may include a gate and a field plate.

Claims

1-20. -20. (canceled)

21. A method of forming a semiconductor device, the method comprising:

forming a first doped well, having a first conductivity type, in a first semiconductor layer having a second conductivity type;

forming a second semiconductor layer having the second conductivity type on the first semiconductor layer;

forming a second doped well of the first conductivity type in the second semiconductor layer;

forming a first doped region having the second conductivity type in the second doped well;

forming a second doped region having the first conductivity type in the second doped well, the second doped region disposed above the first doped region;

forming a third doped region having the first conductivity type in the second semiconductor layer, the third doped region being disposed apart from the second doped well;

forming a fourth doped region having the second conductivity type in the second semiconductor layer, the fourth doped region being formed between the second doped well and the third doped region;

forming a fifth doped region having the second conductivity type in the second semiconductor layer, the fifth doped region being disposed apart from the second doped well region and the fourth doped region;

forming a first insulator on the fourth doped region;

forming a conductive member on the insulator;

forming a source region on the third doped region;

forming a drain region on the second doped well; and

forming a body region on the second semiconductor layer.

22. A method of forming a semiconductor device, the method comprising:

forming a doped well having a first conductivity type in a semiconductor layer;

forming a first doped region having a second conductivity type in the doped well;

forming a second doped region having the first conductivity type in the doped well, the second doped region being disposed above the first doped region;

forming a third doped region having the first conductivity type in the semiconductor layer, the third doped region being disposed apart from the doped well;

forming a fourth doped region having the second conductivity type in the semiconductor layer, the fourth doped region being formed between the doped well and the third doped region;

forming a source region on the third doped region;

forming a drain region on the doped well; and

forming a body region on the semiconductor layer.

23. The method of forming a semiconductor device according to claim 22, the method further comprising:

forming a fifth doped region having the second conductivity type in the semiconductor layer, the fifth doped region being disposed under the body region,

24. The method of forming a semiconductor device according to claim 23, wherein

the steps of forming the fourth doped region and forming the fifth doped region are performed simultaneously.

25. The method of forming a semiconductor device according to claim 23, wherein

the steps of forming the fourth doped region and forming the fifth doped region are performed in a sequential order, either forming the fourth doped region or the fifth doped region first.

26. The method of forming a semiconductor device according to claim 23, wherein

the fourth doped region and the fifth doped region have substantially the same doping concentration.

27. The method of forming a semiconductor device according to claim 23, wherein

the fourth doped region and the fifth doped region have different doping concentrations,

28. The method of forming a semiconductor device according to claim 22, the method further comprising:

forming a field plate connected to at least one of the source region, the drain region, or the body region.

29. The method of forming a semiconductor device according to claim 22, the method further comprising:

forming a first insulator on the fourth doped region; and

forming a conductive member on the first insulator.

30. The method of forming a semiconductor device according to claim 29, the method further comprising:

forming a field plate connected to at least one of the source region, the drain region, the body region, or the conductive member.

31. A method of forming a semiconductor device, the method comprising:

forming a doped well having a first conductivity type in a semiconductor layer;

forming a first doped region having the first conductivity type in the semiconductor layer, the first doped region being disposed apart from the doped well;

forming a second doped region having the second conductivity type in the semiconductor layer, the second doped region being formed between the doped well and the first doped region;

forming a source region on the first doped region;

forming a drain region on the doped well; and

forming a body region on the semiconductor layer,

32. The method of forming a semiconductor device according to claim 31, the method further comprising:

forming a third doped region having the second conductivity type in the doped well; and

forming a fourth doped region having the first conductivity type in the doped well, the fourth doped region being disposed above the third doped region;

33. The method of forming a semiconductor device according to claim 31, the method further comprising:

forming a fifth doped region having the second conductivity type in the semiconductor layer, the fifth doped region being disposed under the body region.

34. The method of forming a semiconductor device according to claim 33, wherein

the steps of forming the second doped region and forming the h doped region are performed simultaneously.

35. The method of forming a semiconductor device according to claim 33, wherein

the steps of forming the second doped region and forming the fifth doped region are performed in a sequential order, either forming the second doped region or the fifth doped region first.

36. The method of forming a semiconductor device according to claim 33, wherein

the second doped region and the fifth doped region have substantially the same doping concentration.

37. The method of forming a semiconductor device according to claim 33, wherein

the second doped region and the fifth doped region have different doping concentrations.

38. The method of forming a semiconductor device according to claim 31, the method further comprising:

forming a field plate connected to at least one of the source region, the drain region, or the body region.

39. The method of forming a semiconductor device according to claim 31, the method further comprising:

forming a first insulator on the second doped region; and

forming a conductive member on the first insulator.

40. The method of forming a semiconductor device according to claim 39, the method further comprising:

forming a field plate connected to at least one of the source region, the drain region, the body region, or the conductive member.