SELF-ALIGNED SHIELDED-GATE TRENCH MOS-CONTROLLED SILICON CARBIDE SWITCH WITH REDUCED MILLER CAPACITANCE AND METHOD OF MANUFACTURING THE SAME

• US 20170213908A1
• Filed: 07/01/2015
• Published: 07/27/2017
• Est. Priority Date: 07/25/2014
• Status: Abandoned Application

• Current Assignee: United Silicon Carbide, Inc. (Qorvo, Inc.)
• Original Assignee: United Silicon Carbide, Inc. (Qorvo, Inc.)
• Inventors: FURSIN, Leonid, BHALLA, Anup
• Application Number:
  US15/329,086
• Publication Number:
  US 20170213908A1
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0834 Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66325 controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Disclosed herein is a shielded-gate silicon carbide trench MOS-controlled switch, such as a MOSFET or IGBT, with a reduced Miller capacitance. The switch disclosed herein can be used in a variety of applications, including high temperature and/or high voltage power conversion.

Claims

1. A silicon carbide trench shielded-gate n-channel MOS-controlled switch with trench-based polysilicon source electrode, comprising:

a. a drift layer of the second conductivity (n-type) formed by homo-epitaxial growth with thickness in the range 1 to 1000 microns;

b. a current-spreading (or carrier storage for IGBT) layer of second conductivity type (n-type), formed on top of the drift layer either by epitaxial growth or ion implantation, with thickness in the range 0.5 to 2 microns;

c. a p-base layer of first conductivity type (p-type), formed on top of the channel layer either by epitaxial growth or ion implantation, with thickness in the range 0.02 to 1 microns;

d. a p-base layer is electrical connection to the top ohmic contact electrode (source of a MOSFET or emitter of an IGBT) via high-dose p+ ion implanted regions at specific region(s) within device active area and top ohmic contact electrode;

e. a top contact layer of the second conductivity type (n-type) formed on top of the base layer either by epitaxial growth or ion implantation, with thickness in the range 0.05 to 0.5 microns;

f. plurality of U-shaped MOS trenches formed in the contact layer, base layer, and current-spreading layer, the each U-shaped MOS trench including;

i. a lower portion below the lower boundary of the p-base layer with rounded bottom surface, and an upper portion above the lower boundary of the p-base layer, a first side surface, and a second side surface;

ii. the trenches extending from the top of the contact layer, through the contact layer, through the p-base, through the current spreading layer; and

the bottom of the trenches being surrounded by the drift layer;

iii. a top ohmic contact electrode, such as source of MOSFET or emitter of IGBT, formed on top of the contact layer;

iv. a MOS gate electrode in the upper portion of the trench between first and second side surfaces, formed with degenerately doped polysilicon, separated from the adjacent silicon carbide p-base layer on MOS trench side-wall with electrically insulating thermally grown 30-100 nm thick MOS gate oxide;

v. a MOS gate electrode being electrically isolated from the top metal overlay with interlayer dielectric, such as a combination of layers including CVD silicon dioxide, CVD silicon nitride and spin-on-dielectric,

vi. a MOS trench-based polysilicon source electrode, made with degenerately doped polysilicon and intended to reduce device Miller capacitance, formed in the lower portion of each individual MOS trench between first and second side surfaces below the MOS gate;

vii. a MOS trench-based polysilicon source electrode being electrically insulated from silicon carbide trench bottom, first and second side surfaces with thick CVD dielectric;

viii. a MOS trench-based degenerately doped polysilicon source electrode being electrically insulated from the MOS gate electrode with thermally grown oxide on polysilicon surface, formed concurrently with thermal MOS gate oxide;

ix. a thickness of thermal oxide on MOS trench-based degenerately doped polysilicon source electrode being at least a factor of 1.5×

thicker than MOS gate oxide on trench first and second side surfaces;

x. a MOS trench-based degenerately doped polysilicon source electrode being electrically connected to the source overlay via raised polysilicon source electrode regions within certain regions in device active area, where MOS gate electrode is not present;

xi. a MOS gate electrode being electrically connected to a gate bonding/probing pad via ohmic contact to raised polysilicon MOS gate layer in certain region within device die;

xii. a first and second side-walls of MOS trenches, comprising MOS channel, all oriented along m-plane (1100) or a-plane (1120) surfaces in 4H-silicon carbide;

g. plurality of U-shaped shielding trenches formed in the contact layer, base layer, and current-spreading layer, the each U-shaped shielding trench including;

i. a rounded bottom surface, a first side surface, and a second side surface;

ii. the shielding trenches extending from the top of the contact layer, through the contact layer, through the p-base, through the current spreading layer; and

the bottom of the trenches being surrounded by the drift layer;

iii. the shielding trenches extending into drift layer by at least 100 nm deeper than MOS trenches;

iv. a top ohmic contact electrode, such as source of MOSFET or emitter of IGBT, formed on top of the contact layer;

v. a shielding trench polysilicon fill, made with degenerately doped polysilicon, formed between first and second side surfaces below the MOS gate;

vi. a shielding trench polysilicon fill being electrically insulated from silicon carbide trench bottom, first and second side surfaces with thick CVD dielectric;

vii. a thick CVD dielectric lining the bottom, first and second surfaces of the shielding trench being deposited concurrently with thick CVD dielectric lining the lower portion of MOS trenches;

viii. a shielding trench polysilicon fill being electrically connected to the source overlay via ohmic contact electrodes formed to the top of polysilicon trench fill;

h. a top metal overlay, connecting individual top ohmic contact electrodes within device die active area;

i. an optional thin thermally grown oxide on the bottom, first and second surfaces of MOS trenches and bottom, first and second surfaces of the shielding trenches, with the thickness of 10-100 nm;

j. a CVD dielectric lining the lower portion of MOS trenches and bottom, first and second surfaces of the shielding trenches is at least factor of 1.5 thicker than the MOS gate oxide;

k. The total portion of device active area occupied by of MOS trenches is at least factor of 2×

larger than the area occupied by shielding trenches;

l. MOS trench-based polysilicon source electrode within lower portion of MOS trenches is deposited concurrently with shielding trench polysilicon fill;

m. a contact and metal overlay formed on the wafer side, opposite to the top contact layer, which is either a drain ohmic contact electrode of a MOSFET or collector of an IGBT;

n. an etched bevel at device edge termination region to reach through contact, p-base and current spreading layers and reaching into drift layer to facilitate electrical connection of the p-base layer to the implanted multi-zone junction termination extension (MJTE), multiple floating guard-rings (MFGR), or combination of both.

2. A self-aligned method of forming a silicon carbide trench shielded-gate n-channel MOS-controlled switch with trench-based polysilicon source electrode of claim 1, comprising:

a. forming a drift layer of the second conductivity (n-type) by homo-epitaxial growth;

b. forming a current-spreading (or carrier storage for IGBT) layer of second conductivity type (n-type) by homo-epitaxial growth, on top of the drift layer either by epitaxial growth or ion implantation;

c. forming a p-base layer of first conductivity type (p-type), formed on top of the channel layer either by epitaxial growth or ion implantation;

d. forming P-base layer electrical connection to the top ohmic contact electrode (source of a MOSFET or emitter of an IGBT) via high-dose p+ ion implanted regions at specific region(s) within device active area, and top ohmic contact electrode;

e. forming a top contact layer of the second conductivity type (n-type) formed on top of the base layer either by epitaxial growth or ion implantation;

f. forming plurality of U-shaped MOS trenches of claim 1 in the contact layer, base layer, and current-spreading layer;

g. ing plurality of U-shaped shielding trenches of claim 1 in the contact layer, base layer, and current-spreading layer

h. forming a top metal overlay, connecting individual top ohmic contact electrodes within device die active area;

i. forming optional thin thermally grown oxide on the bottom, first and second surfaces of MOS trenches and bottom, first and second surfaces of the shielding trenches, with the thickness of 10-100 nm;

j. forming CVD dielectric lining in the lower portion of MOS trenches and bottom, first and second surfaces of the shielding trenches;

k. forming MOS trench-based polysilicon source electrode within lower portion of MOS trenches, by depositing it concurrently with shielding trench polysilicon fill;

l. forming a contact and metal overlay on the wafer side, opposite to the top contact layer, thus forming drain ohmic electrode of a MOSFET or collector of an IGBT;

m. forming an etched bevel at device edge termination region to reach through contact, p-base and current spreading layers and reaching into drift layer to facilitate electrical connection of the p-base layer to the implanted multi-zone junction termination extension (MJTE), multiple floating guard-rings (MFGR), or combination of both.

3. A silicon carbide trench shielded-gate n-channel MOS-controlled switch with trench-based polysilicon source electrode of claim 1, wherein the shielding and active MOS trenches comprise linear arrays of unit cells.

4. A silicon carbide trench shielded-gate n-channel MOS-controlled switch with trench-based polysilicon source electrode of claim 1, wherein the square or rectangular shielding and active MOS trenches are interdigitated.

5. A silicon carbide trench shielded-gate n-channel MOS-controlled switch with trench-based polysilicon source electrode of claim 1, wherein the hexagonal shielding and active MOS trenches are arranged.

6. A silicon carbide trench shielded-gate n-channel MOS-controlled switch with trench-based polysilicon source electrode of claim 1, wherein the circular shielding and active MOS trenches are interdigitated.

7. A silicon carbide trench shielded-gate n-channel MOS-controlled switch with trench-based polysilicon source electrode of claim 1, wherein the switch is an n-channel MOSFET, further comprising:

a. a substrate region of second conductivity type;

b. an epitaxially grown buffer layer of second conductivity type formed between the drift layer and the substrate;

c. a drain ohmic contact electrode, with specific contact resistivity of less than 1 mOhm-cm², formed to the exposed substrate side.

8. A silicon carbide trench shielded-gate n-channel MOS-controlled switch with trench-based polysilicon source electrode of claim 1, wherein the switch is an n-channel insulated-gate bipolar transistor (IGBT), further comprising:

a. a substrate region of first conductivity type formed below epitaxial buffer layers;

b. an optional epitaxially grown buffer layer of first conductivity type formed on the substrate;

c. an epitaxially grown buffer layer of second conductivity type, formed between optional epitaxially grown buffer layer of first conductivity type and the drift layer

d. an epitaxially grown buffer layer of second conductivity type acts as a field-stop in IGBT off-state, when the drift layer is fully depleted in order to support the applied drain-to-source voltage;

e. epitaxial buffer layer and the substrate, both of first conductivity type, provide minority carrier injection into the drift layer in on-state, when IGBT conducts high forward current;

f. a collector ohmic contact electrode, with specific contact resistivity of less than 100 mOhm-cm², formed to the exposed substrate side.

9. A silicon carbide trench shielded-gate n-channel MOS-controlled switch with trench-based polysilicon source electrode of claim 1, wherein the switch is an n-channel insulated-gate bipolar transistor (IGBT), further comprising:

a. original n-type substrate, on which device has been fabricated, has been removed by grinding with wafer front side attached to a standard wafer carrier with conventional low-temperature wafer bond;

b. an ion implanted buffer layer of second conductivity type formed below the drift layer, which acts as a field-stop in IGBT off-state, when the drift layer is fully depleted in order to support the applied drain-to-source voltage;

c. an ion implanted minority carrier injector layer of first conductivity type formed below the field-stop layer;

d. a collector contact layer of first conductivity type formed below the field-stop layer by blanket ion implantation, with total ion dose being at least 10×

higher than total ion dose implanted for minority carrier injector layer;

e. backside ion implanted dopants being activated via non-equilibrium process, such as laser irradiation, after top-side processing being completed;

f. a collector ohmic contact electrode, with specific contact resistivity of less than 100 mOhm-cm², formed via non-equilibrium process, such as laser irradiation, after backside ion implants had been activated.

10. A silicon carbide trench shielded-gate n-channel IGBT switch with trench-based polysilicon source electrode of claim 9, comprising:

a. a heavily doped collector contact regions of first conductivity type formed within continuous injector layer of first conductivity layer by patterned ion implantation using either a shadow mask or photoresist pattern;

b. the total ion dose supplied to the wafer during ion implantation of collector contact regions has to be at least factor 10×

higher than total ion dose supplied during ion implantation for backside injector;

c. the total area of heavily doped collector contact regions being no more than 50% of total backside die area;

d. heavily doped collector contact regions either having stripe or circular patterns.

11. A self-aligned method of forming a trench shielded-gate n-channel MOS-controlled switch with trench-based polysilicon source electrode of claim 7, wherein the switch is an n-channel MOSFET, comprising:

a. forming an epitaxially grown buffer layer of second conductivity type on the original substrate of second conductivity type;

b. forming a drain ohmic contact electrode, with specific contact resistivity of less than 1 mOhm-cm², on the exposed substrate side.

12. A self-aligned method of forming a trench shielded-gate n-channel MOS-controlled switch with trench-based polysilicon source electrode of claim 8, wherein the switch is an n-channel insulated-gate bipolar transistor (IGBT), further comprising:

a. forming an optional epitaxially grown buffer layer of first conductivity type on the original substrate of first conductivity type;

b. forming an epitaxially grown buffer layer of second conductivity type between optional epitaxially grown buffer layer of first conductivity type and the drift layer

c. forming an epitaxially grown buffer layer of second conductivity type acts as a field-stop in IGBT off-state, when the drift layer is fully depleted in order to support the applied drain-to-source voltage;

d. forming epitaxial buffer layer and the substrate, both of first conductivity type, to provide minority carrier injection into the drift layer in on-state, when IGBT conducts high forward current;

e. forming a collector ohmic contact electrode, with specific contact resistivity of less than 100 mOhm-cm², on the exposed substrate side.

13. A self-aligned method of forming a trench shielded-gate n-channel MOS-controlled switch with trench-based polysilicon source electrode of claim 9, wherein the switch is an n-channel insulated-gate bipolar transistor (IGBT), further comprising:

a. removing original n-type substrate, on which device has been fabricated, by grinding with attaching wafer front side to a standard wafer carrier with conventional low-temperature wafer bond;

b. forming ion implanted buffer layer of second conductivity type below the drift layer, which acts as a field-stop in IGBT off-state, when the drift layer is fully depleted in order to support the applied drain-to-source voltage;

c. forming an ion implanted minority carrier injector layer of first conductivity type below the field-stop layer;

d. forming a collector contact layer of first conductivity type formed below the field-stop layer by blanket ion implantation, with total ion dose being at least 10×

higher than total ion dose implanted for minority carrier injector layer;

e. activating backside ion implanted dopants via non-equilibrium process, such as laser irradiation, after top-side processing being completed;

f. forming a collector ohmic contact electrode, with specific contact resistivity of less than 100 mOhm-cm², via backside metal deposition and non-equilibrium process, such as laser irradiation, after backside ion implants had been activated.

14. A self-aligned method of forming a trench shielded-gate n-channel IGBT switch with trench-based polysilicon source electrode of claim 13, further comprising:

a. forming a heavily doped collector contact regions of first conductivity type within continuous injector layer of first conductivity layer by patterned ion implantation using either a shadow mask or photoresist pattern;

b. supplying total ion dose to the wafer during ion implantation of collector contact regions at least factor 10×

higher than total ion dose supplied during ion implantation for backside injector;

c. forming the total area of heavily doped collector contact regions no more than 50% of total backside die area;

d. forming heavily doped collector contact regions either having stripe or circular patterns.

15. The die layout of a silicon carbide trench shielded-gate n-channel MOS-controlled switch with trench-based polysilicon source electrode of claim 1, wherein silicon carbide semiconductor material includes at least one of 4H-silicon carbide, 6H-silicon carbide, or 3C-silicon carbide.

16. A silicon carbide trench shielded-gate n-channel MOS-controlled switch with trench-based polysilicon source electrode of claim 1, wherein a switch has a breakdown voltage rating at maximum operating junction temperature in the range of from about +1 V to about +50,000 V.

17. A circuit comprising the silicon carbide trench shielded-gate n-channel MOS-controlled switch with trench-based polysilicon source electrode of claim 1.

18. A device comprising the circuit of claim 17.

20. A self-aligned method of forming a silicon carbide trench shielded-gate n-channel MOS-controlled switch with trench-based polysilicon source electrode of claim 1, comprising:

forming an n-type drift layer formed by homo-epitaxial growth of silicon carbide with thickness in the range 1 to 1000 microns, over monocrystalline 4H-silicon carbide, or other polytype, substrate;

forming an n-type current-spreading (or carrier storage for IGBT) layer on top of the drift layer by either homo-epitaxial growth or ion implantation, with doping level at least 1.5×

different from the drift layer;

forming plurality of U-shaped active MOS trenches by ICP or RIA etching in silicon carbide, reaching through the current spreading layer, wherein the bottom of the trenches is being surrounded by the drift layer and including;

forming a rounded trench bottom, a first side surface, and a second side surface;

forming first and second side surfaces of MOS trenches, comprising active MOS channels in 4H-silicon carbide, deviating from either along m-plane (1100) or a-plane (1120) surfaces by no more than 13 degrees of arc;

forming a 0.1-1.0 micron thick CVD dielectric lining the bottom of the active MOS trench and in contact with MOS trench-based polysilicon source electrode, being deposited concurrently with thick CVD dielectric lining the bottom, first- and second side surfaces of gate shielding trenches;

electrically insulating MOS trench-based degenerately doped, n- or p-type, polysilicon source (emitter of IGBT) electrode from the MOS gate electrode with thermally grown oxide on polysilicon surface, formed concurrently with MOS gate oxide on first and second active MOS trench side surfaces;

forming a polysilicon trench-based source (emitter of IGBT) electrode, electrically connected to a source (emitter of IGBT) bonding/probing pad via as-deposited or alloyed ohmic contact to raised polysilicon layer in certain region within device die;

forming a degenerately doped, n- or p-type, polysilicon MOS gate electrode, controlling electrical conductivity of active MOS channels within p-type Pbase layers on first- and second side surfaces of active MOS trenches, being electrically connected to a gate bonding/probing pad via as-deposited or alloyed ohmic contact to raised polysilicon MOS gate layer in certain region within device die;

forming plurality of U-shaped gate shielding trenches by ICP or RIA etching in silicon carbide, reaching through the current spreading layer, wherein the bottom of the trenches is being surrounded by the drift layer, and extending into drift layer by at least 100 nm deeper than active MOS trenches, the each U-shaped gate shielding trench including;

forming a rounded trench bottom, first side surface, and a second side surface;

forming first and second side surfaces of shielding trenches, deviating from either m-plane (1100) or a-plane (1120) surfaces in 4H-silicon carbide by no more than 13 degrees of arc;

forming a 0.1-1.0 micron thick CVD dielectric lining the bottom, first and second surfaces of the gate shielding trench, deposited concurrently with thick CVD dielectric lining the lower portion of active MOS trenches;

forming a shielding trench polysilicon fill being electrically connected to the source overlay via as-deposited or alloyed ohmic contact electrodes formed to the top of polysilicon trench fill;

defining the total portion of device active area occupied by active MOS trenches being at least factor of 2×

larger than the area occupied by gate shielding trenches;

forming MOS trench-based polysilicon source electrode within lower portion of active MOS trenches by depositing and degenerately doping, p- or n-type, concurrently with gate-shielding trench polysilicon fill;

21. A silicon carbide trench shielded-gate n-channel MOS-controlled switch with trench-based polysilicon source electrode of claim 1, wherein an etched bevel at device edge termination region is formed to reach into drift layer to facilitate electrical connection of the p-base layer to the implanted multi-zone junction termination extension (MJTE), multiple floating guard-rings (MFGR), or combination of both;

22. A silicon carbide trench shielded-gate n-channel MOS-controlled switch with trench-based polysilicon source electrode of claim 1, wherein the current spreading layer is selectively not implanted into edge termination region, so that planar silicon carbide surface is present within edge-termination region, where p-base layer is in contact with the implanted multi-zone junction termination extension (MJTE), multiple floating guard-rings (MFGR), or combination of both;

23. A silicon carbide trench shielded-gate n-channel MOS-controlled switch with trench-based polysilicon source electrode of claim 1, wherein an optional thermally grown oxide on the bottom, first and second surfaces of MOS trenches and bottom, first and second surfaces of the shielding trenches, with the thickness of 10-100 nm;

24. A self-aligned method of forming a trench shielded-gate n-channel MOS-controlled switch with trench-based polysilicon source electrode of claim 2, wherein an etched bevel at device edge termination region is formed to reach into drift layer to facilitate electrical connection of the p-base layer to the implanted multi-zone junction termination extension (MJTE), multiple floating guard-rings (MFGR), or combination of both;

25. A self-aligned method of forming a trench shielded-gate n-channel MOS-controlled switch with trench-based polysilicon source electrode of claim 2, wherein the current spreading layer is selectively not implanted into edge termination region, so that planar silicon carbide surface is present within edge-termination region, where p-base layer is in contact with the implanted multi-zone junction termination extension (MJTE), multiple floating guard-rings (MFGR), or combination of both;

26. A self-aligned method of forming a trench shielded-gate n-channel MOS-controlled switch with trench-based polysilicon source electrode of claim 2, wherein a sacrificial oxide layer is grown by dry- or wet oxidation and sacrificial oxide being subsequently removed with hydrofluoric acid containing chemical, preceding the growth of MOS gate oxide.

27. The silicon carbide trench shielded-gate n-channel MOS-controlled switch with trench-based polysilicon source electrode of claim 1, wherein the thick CVD dielectric insulating the MOS trench-based polysilicon source electrode, or the thick CVD dielectric insulating the shielding trench polysilicon fill, comprises silicon nitride.

28. The silicon carbide trench shielded-gate n-channel MOS-controlled switch with trench-based polysilicon source electrode of claim 1, wherein the thick CVD dielectric lining the bottom, first, and second surfaces of the shielding trench comprises silicon nitride.

19. A silicon carbide trench shielded-gate n-channel MOS-controlled switch with trench-based polysilicon source electrode, comprising:

an n-type drift layer formed by homo-epitaxial growth of silicon carbide with thickness in the range 1 to 1000 microns, over monocrystalline 4H-silicon carbide, or other polytype, substrate;

an n-type current-spreading (or carrier storage for IGBT) layer, formed on top of the drift layer by either homo-epitaxial growth or ion implantation, with doping level at least 1.5×

different from the drift layer;

plurality of U-shaped active MOS trenches etched in silicon carbide, reaching through the current spreading layer, wherein the bottom of the trenches is being surrounded by the drift layer and including;

a rounded trench bottom, a first side surface, and a second side surface;

a first and second side surfaces of MOS trenches, comprising active MOS channels, deviating from either m-plane (1100) or a-plane (1120) surfaces in 4H-silicon carbide by no more than 13 degrees of arc;

a 0.1-1.0 micron thick CVD dielectric lining the bottom of the active MOS trench and in contact with MOS trench-based polysilicon source electrode, being deposited concurrently with thick CVD dielectric lining the bottom, first- and second side surfaces of gate shielding trenches;

a MOS trench-based degenerately doped, n- or p-type, polysilicon source (emitter of IGBT) electrode being electrically insulated from the MOS gate electrode with thermally grown oxide on polysilicon surface, and formed concurrently with MOS gate oxide on first and second active MOS trench side surfaces;

a polysilicon trench-based source (emitter of IGBT) electrode being electrically connected to a source (emitter of IGBT) bonding/probing pad via as-deposited or alloyed ohmic contact to raised polysilicon layer in certain region within device die;

a degenerately doped, n- or p-type, polysilicon MOS gate electrode, controlling electrical conductivity of active MOS channels within p-type Pbase layers on first- and second side surfaces of active MOS trenches, being electrically connected to a gate bonding/probing pad via as-deposited or alloyed ohmic contact to raised polysilicon MOS gate layer in certain region within device die;

plurality of U-shaped gate shielding trenches etched in silicon carbide, reaching through the current spreading layer, wherein the bottom of the trenches is being surrounded by the drift layer, and extending into drift layer by at least 100 nm deeper than active MOS trenches, the each U-shaped gate shielding trench including;

a rounded trench bottom, first side surface, and a second side surface;

a first and second side surfaces of shielding trenches, deviating from either m-plane (1100) or a-plane (1120) surfaces in 4H-silicon carbide by no more than 13 degrees of arc;

a 0.1-1.0 micron thick CVD dielectric lining the bottom, first and second surfaces of the gate shielding trench, being deposited concurrently with thick CVD dielectric lining the lower portion of active MOS trenches;

a shielding trench polysilicon fill being electrically connected to the source overlay via as-deposited or alloyed ohmic contact electrodes formed to the top of polysilicon trench fill;

The total portion of device active area occupied by active MOS trenches is at least factor of 2×

larger than the area occupied by gate shielding trenches;

MOS trench-based polysilicon source electrode within lower portion of active MOS trenches is deposited and degenerately doped, p- or n-type, concurrently with gate-shielding trench polysilicon fill;