IN-MEMORY DATA STORAGE WITH ADAPTIVE MEMORY FAULT TOLERANCE

• US 20170220441A1
• Filed: 01/27/2017
• Published: 08/03/2017
• Est. Priority Date: 02/03/2016
• Status: Active Grant

• Current Assignee: ScaleFlux
• Original Assignee: ScaleFlux
• Inventors: Zhang, Tong, Zhong, Hao, Sun, Fei, Liu, Yang
• Granted Patent: US 10,534,664 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G06F 11/1092 Rebuilding, e.g. when physically replacing a failing disk
• CPC Class Codes: G06F 11/2094 Redundant storage or storage space G06F11/2056 takes precedence

Abstract

A storage aware memory controller for managing a physical storage system. A described controller: a system for mapping physical memory space into a memory region and a storage region; a system for applying different error protections schemes, in which a fine-grained memory fault tolerance scheme is applied to data in the memory region and a course-grained memory fault tolerance scheme is applied to data in the storage region; and a storage file system that includes a mapping table for mapping logical addresses to physical addresses for data stored in the storage region.

Claims

1. A storage aware memory controller for in-memory data processing, comprising:

a system for mapping physical memory space into a memory region and a storage region;

a system for applying different error protections schemes, in which a fine-grained memory fault tolerance scheme is applied to data in the memory region and a course-grained memory fault tolerance scheme is applied to data in the storage region; and

a storage file system that includes a mapping table for mapping logical addresses to physical addresses for data stored in the storage region.

2. The storage aware memory controller of claim 1, wherein the storage region includes a first partition for 1-bit/cell data storage and a second partition for m-bit/cell data storage, wherein m is greater than 1.

3. The storage aware memory controller of claim 2, wherein the m-bit/cell data storage partition utilizes a course grained memory fault tolerance scheme that is relatively stronger than that used for 1-bit/cell data storage.

4. The storage aware memory controller of claim 3, wherein a the storage file system includes a first mapping table for mapping data in the 1-bit/cell data storage partition to a physical address and a second mapping table for mapping data in the m-bit/cell data storage partition to a physical address.

5. The storage aware memory controller of claim 1, wherein the mapping table utilizes a logical address that includes a virtual block ID and block index.

6. The storage aware memory controller of claim 2, further comprising logic for moving data between and among the memory region, 1-bit/cell data storage partition, and m-bit/cell data storage partition.

7. The storage aware memory controller of claim 1, wherein the fine-grained memory fault tolerance scheme provides access patterns of 8-16 bytes, and the course-grained memory fault tolerance scheme provides access patterns of 512-4096 bytes.

8. A memory system comprising:

a physical memory; and

a storage aware memory controller for in-memory data processing, wherein the storage aware memory controller includes;

a system for mapping the physical memory into a memory region and a storage region;

a system for applying different error protections schemes, in which a fine-grained memory fault tolerance scheme is applied to data in the memory region and a course-grained memory fault tolerance scheme is applied to data in the storage region; and

a storage filesystem that includes a mapping table for mapping logical addresses to physical addresses for data stored in the storage region.

9. The memory system of claim 8, wherein the storage region includes a first partition for 1-bit/cell data storage and a second partition for m-bit/cell data storage, wherein m is greater than 1.

10. The memory system of claim 9, wherein the m-bit/cell data storage partition utilizes a course grained memory fault tolerance scheme that is relatively stronger than that used for 1-bit/cell data storage.

11. The memory system of claim 10, wherein the storage filesystem includes a first mapping table for mapping data in the 1-bit/cell data storage partition to a physical address and a second mapping table for mapping data in the m-bit/cell data storage partition to a physical address.

12. The memory system of claim 8, wherein the mapping table utilizes a logical address that includes a virtual block ID and block index.

13. The memory system of claim 9, further comprising logic for moving data between and among the memory region, 1-bit/cell data storage partition, and m-bit/cell data storage partition.

14. The memory system of claim 8, wherein the fine-grained memory fault tolerance scheme provides access patterns of 8-16 bytes, and the course-grained memory fault tolerance scheme provides access patterns of 512-4096 bytes.

15. Computer programming logic stored in a computer readable storage medium, which when executed by a processing core, provides storage aware memory control for in-memory data processing, and comprises:

program logic for mapping physical memory space into a memory region and a storage region;

program logic for applying different error protections schemes, in which a fine-grained memory fault tolerance scheme is applied to data in the memory region and a course-grained memory fault tolerance scheme is applied to data in the storage region; and

program logic that implements a mapping table for mapping logical addresses to physical addresses for data stored in the storage region.

16. The computer program logic of claim 15, wherein the storage region includes a first partition for 1-bit/cell data storage and a second partition for m-bit/cell data storage, wherein m is greater than 1.

17. The computer programming logic of claim 16, wherein the m-bit/cell data storage partition utilizes a course grained memory fault tolerance scheme that is relatively stronger than that used for 1-bit/cell data storage.

18. The computer programming logic of claim 16, wherein the mapping table includes a first mapping table for mapping data in the 1-bit/cell data storage partition to a physical address and a second mapping table for mapping data in the m-bit/cell data storage partition to a physical address.

19. The computer programming logic of claim 15, wherein the mapping table utilizes a logical address that includes a virtual block ID and block index.

20. The computer programming logic of claim 16, further comprising program logic for moving data between and among the memory region, 1-bit/cell data storage partition, and m-bit/cell data storage partition.