WRITE OPERATIONS TO NON-VOLATILE MEMORY

• US 20170220478A1
• Filed: 06/23/2015
• Published: 08/03/2017
• Est. Priority Date: 08/04/2014
• Status: Active Grant

• Current Assignee: Arm Limited (SoftBank Group Corp.)
• Original Assignee: Arm Limited (SoftBank Group Corp.)
• Inventors: GRISENTHWAITE, Richard Roy, SAIDI, Ali Ghassan
• Granted Patent: US 11,429,532 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 12/0891 using clearing, invalidating or resetting means
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 12/126 with special data handling, e.g. priority of data or instructions, handling errors or pinning
• CPC Class Codes: G06F 2212/202 Non-volatile memory
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: G06F 2212/65 Details of virtual memory and virtual address translation
• CPC Class Codes: G06F 9/30 Arrangements for executing machine instructions, e.g. instruction decode for executing microinstructions G06F9/22
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30076 to perform miscellaneous control operations, e.g. NOP
• CPC Class Codes: G06F 9/46 Multiprogramming arrangements

Abstract

An apparatus for processing data and a method of data processing are provided. A processor core in the apparatus performs data processing operations in response to a sequence of instructions, including write operations which write data items to a non-volatile memory. A write-back cache stores local copies of the data items retrieved from the memory and written to the memory by the processor core. A storage unit is provided which stores indications of the write operations initiated by the processor core and the processor core is configured to respond to an end instruction by causing the local copies of data items which are the subject of the write operations by the processor core, and for which an indication is stored in the storage unit, to be cleaned from the write-back cache to the memory. The indications of the write operations stored in the storage unit are then cleared.

Claims

1. Apparatus for processing data comprising:

a processor core capable of performing data processing operations in response to a sequence of instructions, wherein the data processing operations comprise read operations which retrieve data items from a memory and write operations which write data items to the memory, wherein the memory is a non-volatile memory;

a write-back cache capable of storing local copies of the data items retrieved from the memory and written to the memory by the processor core when executing the sequence of instructions; and

a storage unit capable of storing indications of the write operations initiated by the processor core, and

the processor core is capable of responding to an end instruction in the sequence of instructions by;

causing the local copies of data items which are the subject of the write operations by the processor core and for which an indication is stored in the storage unit to be cleaned from the write-back cache to the memory; and

clearing the indications of the write operations stored in the storage unit.

2. The apparatus as claimed in claim 1, wherein the non-volatile memory is byte-addressable.

3. The apparatus as claimed in claim 1, wherein the processor core is further capable of causing the indications of the write operations initiated by the processor core to be stored in the storage unit after a begin instruction in the sequence of instructions.

4. The apparatus as claimed in claim 3, wherein the processor core is capable of only performing a write operation to a predetermined portion of the memory if a pending write instruction specifying the predetermined portion of the memory is preceded by the begin instruction and followed by the end instruction.

5. The apparatus as claimed in claim 3, wherein the processor core is capable of preventing a write operation to a predetermined portion of the memory from being performed if a pending write instruction specifying the predetermined portion of the memory is not preceded by the begin instruction and followed by the end instruction.

6. The apparatus as claimed in claim 3, wherein the processor core is capable of responding to the end instruction and a subsequent begin instruction in the sequence of instructions by causing the subsequent begin instruction in the sequence of instructions to stall until the end instruction has completed.

7. The apparatus as claimed in claim 3, wherein the processor core is capable of responding to the end instruction and a subsequent memory operation instruction in the sequence of instructions by causing the subsequent memory operation instruction in the sequence of instructions to stall until the end instruction has completed.

8. The apparatus as claimed in claim 1, wherein the processor core is capable of responding to the end instruction and a subsequent instruction in the sequence of instructions by causing the subsequent instruction in the sequence of instructions to stall until the end instruction has completed.

9. The apparatus as claimed in claim 1, wherein the storage unit is a first-in-first-out storage unit.

10. The apparatus as claimed in claim 9, wherein the processor core comprises the first-in-first-out storage unit.

11. The apparatus as claimed in claim 1, wherein the storage unit is provided by the write-back cache and the indications of the write operations initiated by the processor core are stored as markers associated with cache lines stored in the write-back cache, wherein setting of a marker of the markers indicates if a local copy of a data item forming at least part of a cache line of the cache lines is the subject of the write operations by the processor core.

12. The apparatus as claimed in claim 1, wherein the storage unit is capable of storing at least partial memory addresses of the write operations initiated by the processor core as the indications.

13. The apparatus as claimed in claim 1, wherein the indications stored in the storage unit indicate at least one cache block where data items corresponding to the write operations are stored in the write-back cache.

14. The apparatus as claimed in claim 1, wherein the processor core is further capable of referencing a page table to determine virtual-to-physical memory address mappings, each entry in the page table comprises a flag to indicate if that entry corresponds to a predetermined memory address space, and the processor core is capable of causing indications of write operations to the predetermined memory address space initiated by the processor core to be stored in the storage unit.

15. The apparatus as claimed in claim 3, wherein the processor core is capable of responding to an encoding within the begin instruction to stall any instructions which follow the end instruction until a controller in the memory acknowledges receipt of a command to commit the local copies of data items cleaned from the write-back cache to the memory.

16. The apparatus as claimed in claim 3, wherein the processor core is capable of responding to an encoding within the begin instruction to stall any instructions which follow the end instruction until a controller in the memory indicates that the local copies of data items cleaned from the write-back cache to the memory have been committed to the memory.

17. The apparatus as claimed in claim 1, further capable of, in response to a clean condition to cause at least one local copy of the local copies stored in the write-back cache which is the subject of at least one write operation by the processor core and for which an indication is stored in the storage unit to be cleaned from the write-back cache to the memory and to clear at least one corresponding indication of the at least one write operation stored in the storage unit.

18. The apparatus as claimed in claim 17, wherein the clean condition is satisfied when the storage unit is full.

19. The apparatus as claimed in claim 17, wherein the clean condition is satisfied when a local copy stored in the write-back cache is evicted to the memory.

20. The apparatus as claimed in claim 17, wherein the clean condition is satisfied when a local copy stored in the write-back cache is snooped by a cache coherence mechanism and for which an indication is stored in the storage unit.

21. The apparatus as claimed in claim 20, wherein the write-back cache is capable of storing clean-on-snoop markers associated with cache lines stored in the write-back cache, wherein setting of a clean-on-snoop marker indicates that a corresponding indication is stored in the storage unit.

22. The apparatus as claimed in claim 1, wherein the storage unit is a content-addressable storage unit.

23. A method of processing data comprising the steps of:

performing data processing operations in response to a sequence of instructions, wherein the data processing operations comprise read operations which retrieve data items from a memory and write operations which write data items to the memory, wherein the memory is a non-volatile memory;

storing local copies in a write-back cache of the data items retrieved from the memory and written to the memory when executing the sequence of instructions;

storing indications of the write operations initiated in the performing data processing operation step; and

responding to an end instruction in the sequence of instructions by;

causing the local copies of data items which are the subject of the write operations and for which an indication has been stored in the storing local copies step to be cleaned from the write-back cache to the memory; and

clearing the indications of the write operations stored in the storing indications step.

24. Apparatus for processing data comprising:

means for performing data processing operations in response to a sequence of instructions, wherein the data processing operations comprise read operations which retrieve data items from a memory and write operations which write data items to the memory, wherein the memory is a non-volatile memory;

means for storing local copies of the data items retrieved from the memory and written to the memory when executing the sequence of instructions, wherein the means for storing has a write-back configuration with respect to the memory;

means for storing indications of the write operations initiated by the means for performing data processing operations; and

means for responding to an end instruction in the sequence of instructions which;

causes the local copies of data items which are the subject of the write operations and for which an indication has been stored by the means for storing local copies to be cleaned from the write-back cache to the memory; and

clears the indications of the write operations stored in the means for storing indications.