MASSIVELY PARALLEL COMPUTER, ACCELERATED COMPUTING CLUSTERS, AND TWO-DIMENSIONAL ROUTER AND INTERCONNECTION NETWORK FOR FIELD PROGRAMMABLE GATE ARRAYS, AND APPLICATIONS

• US 20170220499A1
• Filed: 01/04/2017
• Published: 08/03/2017
• Est. Priority Date: 01/04/2016
• Status: Abandoned Application

• Current Assignee: Grady Research, Inc.
• Original Assignee: Grady Research, Inc.
• Inventors: Gray, Jan Stephen
• Application Number:
  US15/398,701
• Publication Number:
  US 20170220499A1
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/36 for access to common bus or bus system
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: H04L 49/109 Integrated on microchip, e.g. switch-on-chip

Abstract

An embodiment of a massively parallel computing system comprising a plurality of processors, which may be subarranged into clusters of processors, and interconnected by means of a configurable directional 2D router for Networks on Chips (NOCs) is disclosed. The system further comprises diverse high bandwidth external I/O devices and interfaces, which may include without limitation Ethernet interfaces, and dynamic RAM (DRAM) memories. The system is designed for implementation in programmable logic in FPGAs, but may also be implemented in other integrated circuit technologies, such as non-programmable circuitry, and in integrated circuits such as application-specific integrated circuits (ASICs). The system enables the practical implementation of diverse FPGA computing accelerators to speed up computation for example in data centers or telecom networking infrastructure. The system uses the NOC to interconnect processors, clusters, accelerators, and/or external interfaces. A great diversity of NOC client cores, for communication amongst various external interfaces and devices, and on-chip interfaces and resources, may be coupled to a router in order to efficiently communicate with other NOC client cores. The system, router, and NOC enable feasible FPGA implementation of large integrated systems on chips, interconnecting hundreds of client cores over high bandwidth links, including compute and accelerator cores, industry standard IP cores, DRAM/HBM/HMC channels, PCI Express channels, and 10G/25G/40G/100G/400G networks.

Claims

1-78. -78. (canceled)

79. An integrated circuit, comprising:

cluster circuits;

a first one of the cluster circuits including

a first cluster-input bus,

a first cluster-output bus,

a first computing circuit, and

a first interface circuit coupled to the computing circuit, the cluster-input bus, and the cluster-output bus, and configured

to receive, from the computing circuit, a request to send a message that includes payload data,

to generate, in response to the request, an outgoing message that includes a destination indicator and the payload data, and

to cause the outgoing message to be provided on the cluster-output bus; and

a first interconnection network including

routers each coupled to a respective one of the cluster circuits, and

a first one of the routers coupled to the first one of the cluster circuits and including a first routing circuit configured to provide the outgoing message to a second one of the cluster circuits corresponding to the destination indicator.

80. The integrated circuit of claim 79 wherein the first computing circuit includes one or more instruction-executing computing cores.

83. The integrated circuit of claim 79 wherein the first computing circuit includes one or more non-instruction-executing accelerator circuits.

85. The integrated circuit of claim 79 wherein the first routing circuit is further configured:

to determine whether an incoming message identifies the first one of the cluster circuits as a destination of the incoming message; and

to provide at least a portion of the incoming message on the first cluster-input bus if the first router circuit determines that the incoming message identifies the first one of the cluster circuits as the destination of the incoming message.

86. The integrated circuit of claim 79 wherein the first one of the routers further includes:

a first router-input bus coupled to the first cluster-output bus;

a first router-output bus; and

wherein the first routing circuit is configured to

receive the outgoing message on the first router-input bus, and

to provide, via the first router output bus, the outgoing message to the second one of the cluster circuits corresponding to the destination indicator.

87. The integrated circuit of claim 86 wherein the first router-output bus is coupled to the first cluster-input bus.

89. The integrated circuit of claim 79 wherein the first routing circuit is configured to multicast the outgoing message to the second one of the cluster circuits and to one or more third ones of the cluster circuits corresponding to the destination indicator.

91. The integrated circuit of claim 79 wherein the first one of the routers further includes:

a first router-output bus coupled to the first cluster-input bus; and

wherein the first routing circuit is configured to indicate to the first one of the cluster circuits that a message on the first router-output bus is an incoming message for the first one of the cluster circuits; and

wherein the first interface circuit is configured to cause the incoming message to be coupled from the first router-output bus to the first cluster-input bus in response to the indication.

92. The integrated circuit of claim 79 wherein the first interconnection network includes a ring interconnection network.

93. The integrated circuit of claim 79 wherein the first interconnection network includes a torus interconnection network

97. The integrated circuit of claim 79, further comprising:

a second one of the routers coupled to the second one of the cluster circuits and including a second routing circuit;

wherein the first computing circuit of the first one of the cluster circuits includes first instruction-executing computing cores, one of the first instruction-executing computing cores configured to generate the payload data;

wherein the second one of the cluster circuits includes a second computing circuit having second instruction-executing computing cores and includes a second interface circuit;

wherein the first interface circuit of the first one of the cluster circuits is configured to generate the destination indicator to indicate one of the second instruction-executing computing cores of the second one of the cluster circuits;

wherein the first routing circuit of the first one of the routers is configured to provide the outgoing message to the second one of the routers;

wherein the second routing circuit of the second one of the routers is configured to provide the outgoing message to the second one of the cluster circuits as an incoming message; and

wherein the second interface circuit of the second one of the cluster circuits is configured to provide the payload data of the incoming message to the one of the second instruction-executing computing cores indicated by the destination indicator.

98. The integrated circuit of claim 79, further comprising:

a second one of the routers coupled to the second one of the cluster circuits and including a second routing circuit;

wherein the first computing circuit of the first one of the cluster circuits includes first instruction-executing computing cores, one of the first instruction-executing computing cores configured to generate the payload data;

wherein the second one of the cluster circuits includes a second computing circuit having second configurable accelerators and includes a second interface circuit;

wherein the first interface circuit of the first one of the cluster circuits is configured to generate the destination indicator to indicate one of the second configurable accelerators of the second one of the cluster circuits;

wherein the first routing circuit of the first one of the routers is configured to provide the outgoing message to the second one of the routers;

wherein the second routing circuit of the second one of the routers is configured to provide the outgoing message to the second one of the cluster circuits as an incoming message; and

wherein the second interface circuit of the second one of the cluster circuits is configured to provide the payload data of the incoming message to the one of the second configurable accelerators indicated by the destination indicator.

100. The integrated circuit of claim 79, further comprising:

a second one of the routers coupled to the second one of the cluster circuits and including a second routing circuit;

wherein the first computing circuit of the first one of the cluster circuits includes first configurable accelerators, one of the first configurable accelerators configured to generate the payload data;

wherein the second one of the cluster circuits includes a second computing circuit having second configurable accelerators and includes a second interface circuit;

wherein the first interface circuit of the first one of the cluster circuits is configured to generate the destination indicator to indicate one of the second configurable accelerators of the second one of the cluster circuits;

wherein the first routing circuit of the first one of the routers is configured to provide the outgoing message to the second one of the routers;

wherein the second routing circuit of the second one of the routers is configured to provide the outgoing message to the second one of the cluster circuits as an incoming message; and

the second interface circuit of the second one of the cluster circuits is configured to provide the payload data of the incoming message to the one of the second configurable accelerators indicated by the destination indicator.

101. The integrated circuit of claim 79, further comprising:

a second one of the routers coupled to the second one of the cluster circuits and including a second routing circuit;

wherein the first computing circuit of the first one of the cluster circuits includes a first instruction-executing computing core and a first configurable accelerator, one of the first instruction-executing computing core and the first configurable accelerator configured to generate the payload data;

wherein the second one of the cluster circuits includes a second computing circuit having a second instruction-executing computing core and a second configurable accelerator, and includes a second interface circuit;

wherein the first interface circuit of the first one of the cluster circuits is configured to generate the destination indicator to indicate one of the second instruction-executing computing core and the second configurable accelerator of the second one of the cluster circuits;

wherein the first routing circuit of the first one of the routers is configured to provide the outgoing message to the second one of the routers;

wherein the second routing circuit of the second one of the routers is configured to provide the outgoing message to the second one of the cluster circuits as an incoming message; and

the second interface circuit of the second one of the cluster circuits is configured to provide the payload data of the incoming message to the one of the second instruction-executing computing core and the second configurable accelerator indicated by the destination indicator.

103. The integrated circuit of claim 79 wherein the first interconnection network includes a network bus to which the routers are coupled, the network bus wide enough to carry all bits of the output message simultaneously.

104. The integrated circuit of claim 79 wherein the first interconnection network includes a router configured for coupling to a circuit that is external to the integrated circuit.

81-82. -82. (canceled)

84. (canceled)

88. (canceled)

90. (canceled)

94-96. -96. (canceled)

99. (canceled)

102. (canceled)

105-107. -107. (canceled)

108. A non-transitory computer-readable medium storing configuration data that, when received by a field-programmable gate array, causes the field-programmable gate array to instantiate:

cluster circuits;

a first one of the cluster circuits including

a first cluster-input bus,

a first cluster-output bus,

a first computing circuit, and

a first interface circuit coupled to the computing circuit, the cluster-input bus, and the cluster-output bus, and configured

to receive, from the computing circuit, a request to send a message that includes payload data,

to generate, in response to the request, an outgoing message that includes a destination indicator and the payload data, and

to cause the outgoing message to be provided on the cluster-output bus; and

a first interconnection network including

routers each coupled to a respective one of the cluster circuits, and

a first one of the routers coupled to the first one of the cluster circuits and including a first routing circuit configured to provide the outgoing message to a second one of the cluster circuits corresponding to the destination indicator.

109. A method, comprising:

generating intermediate data with a first computing circuit of a first cluster circuit on an integrated circuit, the first computing circuit including one or more first processors each including a respective first instruction-executing computing core or a respective first configurable accelerator, together the one or more first processors including multiple first instruction-executing computing cores or at least one first configurable accelerator;

sending the intermediate data from the first cluster circuit to a second cluster circuit on the integrated circuit via an interconnection network on the integrated circuit; and

generating, in response to the intermediate data, first output data with a second computing circuit of the second cluster circuit, the second computing circuit including one or more second processors each including a respective second instruction-executing computing core or a respective second configurable accelerator, together the one or more second processors including multiple second instruction-executing computing cores or at least one second configurable accelerator.

110. The method of claim 109, further comprising:

receiving input data at the first cluster circuit via the interconnection network; and

wherein generating the intermediate data includes generating the intermediate data with the first computing circuit in response to the input data.

111. The method of claim 110 wherein receiving the input data includes receiving the input data from a third cluster circuit on the integrated circuit via the interconnection network.

112. The method of claim 110 wherein receiving the input data includes receiving the input data from a source circuit via the interconnection network, the source circuit external to the integrated circuit.

117. The method of claim 109, further comprising:

the first cluster circuit generating a message that includes the intermediate data and a destination indicator that indicates the second cluster circuit; and

wherein sending the intermediate data includes

sending the message from the first cluster circuit to a first router of the interconnection network,

sending the message from the first router to a second router of the interconnection network in a number of clock cycles equal to a number of routers through which the message propagates, the number inclusive of the first router and the second router, and

sending the message from the second router to the second cluster circuit.

121. The method of claim 109, further comprising:

sending the intermediate data from the first cluster circuit to a third cluster circuit on the integrated circuit via the interconnection network; and

generating, in response to the intermediate data, second output data with a third computing circuit of the third cluster circuit.

122. The method of claim 109, further comprising:

wherein sending the intermediate data includes sending a first portion of the intermediate data from the first cluster circuit to the second cluster circuit;

sending a second portion of the intermediate data from the first cluster circuit to a third cluster circuit on the integrated circuit via the interconnection network;

wherein generating the first output data includes generating, in response to the first portion of the intermediate data, the first output data with the second computing circuit; and

generating, in response to the second portion of the intermediate data, second output data with a third computing circuit of the third cluster circuit.

125. The method of claim 109, further comprising:

wherein sending the intermediate data includes sending a first portion of the intermediate data from the first cluster circuit to the second cluster circuit;

sending a second portion of the intermediate data from the first cluster circuit to a third cluster circuit on the integrated circuit via the interconnection network;

wherein generating the first output data includes generating, in response to the first portion of the intermediate data, the first output data with a first configurable accelerator of the second computing circuit, the first configurable accelerator having a configuration; and

generating, in response to the second portion of the intermediate data, second output data with a third configurable accelerator of a third computing circuit of the third cluster circuit, the third configurable accelerator having the configuration.

126. The method of claim 109, further comprising:

writing the intermediate data from the first computing circuit into a memory circuit of the first cluster circuit;

reading the intermediate data from the memory circuit onto a first cluster-output bus of the first cluster circuit; and

wherein sending the intermediate data includes coupling the intermediate data from the first cluster-output bus to a bus of the interconnection network.

127. The method of claim 109, further comprising:

writing the intermediate data from a bus of the interconnection network into a memory circuit of the second cluster circuit;

at least one of the second processors of the second computing circuit reading the intermediate data from the memory;

wherein generating the first output data includes at least one of the second processors of the second computing circuit generating the output data; and

writing the first output data from at least one of the second processors of the second computing circuit to the memory.

130. The method of claim 109 wherein the first cluster circuit, the second cluster circuit, and the interconnection network are instantiated on a field-programmable gate array.

133. The method of claim 109 wherein:

at least a portion of one of the first cluster circuit, the second cluster circuit, and the interconnection network is instantiated on a field-programmable gate array; and

at least another potion of one of the first cluster circuit, the second cluster circuit, and the interconnection network is disposed on the field-programmable gate array.

113-116. -116. (canceled)

118-120. -120. (canceled)

123-124. -124. (canceled)

128-129. -129. (canceled)

131-132. -132. (canceled)

134-135. -135. (canceled)

136. A non-transitory computer-readable medium storing configuration data that, when received by a field-programmable gate array, causes the field-programmable gate array:

to generate intermediate data with a first computing circuit of a first cluster circuit on an integrated circuit, the first computing circuit including one or more first processors each including a respective first instruction-executing computing core or a respective first configurable accelerator, together the one or more first processors including multiple first instruction-executing computing cores or at least one first configurable accelerator;

to send the intermediate data from the first cluster circuit to a second cluster circuit on the integrated circuit via an interconnection network on the integrated circuit; and

to generate, in response to the intermediate data, first output data with a second computing circuit of the second cluster circuit, the second computing circuit including one or more second processors each including a respective second instruction-executing computing core or a respective second configurable accelerator, together the one or more second processors including multiple second instruction-executing computing cores or at least one second configurable accelerator.