LARGE CLUSTER PERSISTENCE DURING PLACEMENT OPTIMIZATION OF INTEGRATED CIRCUIT DESIGNS

• US 20170220722A1
• Filed: 08/11/2016
• Published: 08/03/2017
• Est. Priority Date: 01/29/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: KIM, MYUNG-CHUL, RAMJI, SHYAM, VILLARRUBIA, PAUL G., VISWANATHAN, NATARAJAN
• Granted Patent: US 10,140,409 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

The disclosed herein relates to method for persistence during placement optimization of an integrated circuit design. The method comprises performing cluster operation by grouping of a plurality of cells into a plurality of mobs. The method further comprises performing a spreading operation by moving the plurality of mobs and the plurality of cells simultaneously to optimize empty space of the integrated circuit design.

Claims

1. A method for high physical persistence during placement optimization of an integrated circuit design, comprising:

performing, by a processor coupled to a memory, cluster operation by grouping of a plurality of cells into a plurality of mobs; and

performing, by the processor, a spreading operation by a utilizing a force-directed placement to move the plurality of mobs and the plurality of cells simultaneously to optimize empty space of the integrated circuit design.

2. The method of claim 1, wherein each mob is a cluster of a portion of the plurality of cells that share a common characteristic.

3. The method of claim 2, wherein the common characteristic is a connection within netlist, a name hierarchy, or a clock domain.

4. The method of claim 1, wherein the spreading operation achieves the high physical persistence by:

identifying for each of the plurality of mobs a plurality of variables comprising a spreading force, a mob center of gravity force, and a mob center of gravity direction force, and

adding for each of the plurality of mobs the spreading force, the mob center of gravity force, and the mob center of gravity direction force based on sigmoid force weight scheduling.

5. The method of claim 4, comprising:

performing two-level sigmoid force weight scheduling to balance the high physical persistence of the plurality of mobs and overall spreading;

periodically measuring the high physical persistence and mob-specific center of gravity uplift force of the plurality of mobs; and

performing hierarchical mob-based placement by generating and placing super-mobs and generating sub-mobs.

6. The method of claim 1, comprising:

periodically measuring the high physical persistence of the plurality of mobs; and

adding an additional center of gravity force to further compact weak mobs of the plurality of mobs based on the measuring.