ELECTROSTATIC DISCHARGING CIRCUIT AND DISPLAY DEVICE INCLUDING THE SAME

• US 20170221417A1
• Filed: 01/27/2017
• Published: 08/03/2017
• Est. Priority Date: 02/01/2016
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: CHO, SE-HYOUNG, KANG, JANG-MI, KIM, KYUNG-HOON, JUNG, MEE-HYE
• Granted Patent: US 10,839,750 B2
• Time in Patent Office: Days
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2330/04 Display protection
• CPC Class Codes: G09G 2330/06 Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/3258 with pixel circuitry controlling the voltage across the light-emitting element
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence

Abstract

An electrostatic discharging circuit includes a first transistor including a first electrode electrically connected to a signal line, a second electrode receiving a first voltage, and a first gate electrode electrically connected to a first node. A second transistor includes a third electrode electrically connected to the signal line, a fourth electrode electrically connected to the first node, and a second gate electrode electrically connected to the first node. A first capacitor receives the first voltage and is electrically connected to the first node.

Claims

1. An electrostatic discharging circuit comprising:

a first transistor including a first electrode electrically connected to a signal line, a second electrode receiving a first voltage, and a first gate electrode electrically connected to a first node;

a second transistor including a third electrode electrically connected to the signal line, a fourth electrode electrically connected to the first node, and a second gate electrode electrically connected to the first node; and

a first capacitor receiving the first voltage and electrically connected to the first node.

2. The electrostatic discharging circuit of claim 1, wherein the first capacitor stores a second threshold voltage of the second transistor.

3. The electrostatic discharging circuit of claim 1, wherein the first transistor clamps a signal based on the first voltage, and

wherein the signal is provided through the signal line.

4. The electrostatic discharging circuit of claim 1, wherein a second threshold voltage of the second transistor is greater than a first threshold voltage of the first transistor.

5. The electrostatic discharging circuit of claim 1, wherein a length of a second channel of the second transistor is longer than a length of a first channel of the first transistor.

6. The electrostatic discharging circuit of claim 1, wherein the second transistor includes:

a first sub transistor including a fifth electrode electrically connected to a third node, a sixth electrode electrically connected to the first node, and a third gate electrode electrically connected to the first node; and

a second sub transistor including a seventh electrode electrically connected to the signal line, an eighth electrode electrically connected to the third node, and a fourth gate electrode electrically connected to the first node.

7. The electrostatic discharging circuit of claim 1, wherein a width of a second channel of the second transistor is narrower than a width of a first channel of the first transistor.

8. The electrostatic discharging circuit of claim 1, wherein the first transistor includes:

a first auxiliary transistor including a ninth electrode electrically connected to the signal line, a tenth electrode receiving the first voltage, and a fifth gate electrode electrically connected to the first node; and

a second auxiliary transistor including an eleventh electrode electrically connected to the signal line, a twelfth electrode receiving the first voltage, and a sixth gate electrode electrically connected to the first node.

9. The electrostatic discharging circuit of claim I further comprising:

a third transistor including a thirteenth electrode electrically connected to a second voltage, a fourteenth electrode electrically connected to the signal line, and a seventh gate electrode electrically connected to a second node;

a fourth transistor including a fifteenth electrode electrically connected to the second voltage, a sixteenth electrode electrically connected to the second node, and an eighth gate electrode electrically connected to the second node; and

a second capacitor receiving the second voltage and electrically connected to the second node.

10. The electrostatic discharging circuit of claim 9, wherein the second capacitor stores a fourth threshold voltage of the fourth transistor.

11. The electrostatic discharging circuit of claim 9, wherein the third transistor clamps a signal based on the second voltage, and

wherein the signal is provided through the signal line.

12. The electrostatic discharging circuit of claim 9, wherein a voltage level of the first voltage is higher than a voltage level of the second voltage.

13. The electrostatic discharging circuit of claim 9, wherein a fourth channel of the fourth transistor is longer than a third channel of the third transistor.

14. The electrostatic discharging circuit of claim 9, wherein the fourth transistor includes:

a third sub transistor including a seventeenth electrode electrically connected to a fourth node, an eighteenth electrode electrically connected to the second node, and a ninth gate electrode electrically connected to the second node; and

a fourth sub transistor including an nineteenth electrode electrically connected to the second voltage, a twentieth electrode electrically connected to the fourth node, and a tenth gate electrode electrically connected to the second node.

15. The electrostatic discharging circuit of claim 9, wherein a fourth channel of the fourth transistor is narrower than a third channel of the third transistor.

16. The electrostatic discharging circuit of claim 9, wherein the third transistor includes;

a third auxiliary transistor including a twenty-first electrode receiving the second voltage, a twenty-second electrode electrically connected to the signal line, and an eleventh gate electrode electrically connected to the second node; and

a fourth auxiliary transistor including a twenty-third electrode receiving the second voltage, a twenty-fourth electrode electrically connected to the signal line, and a twelfth gate electrode electrically connected to the second node.

17. A display panel comprising:

a pixel;

a pad receiving a signal from an external source;

a signal line transferring the signal to the pixel; and

an electrostatic discharging circuit disposed adjacent to the pad,

wherein the electrostatic discharging circuit includes;

a first transistor including a first electrode electrically connected to the signal line, a second electrode receiving a first voltage, and a first gate electrode electrically connected to a first node;

a second transistor including a third electrode electrically connected to the signal line, a fourth electrode electrically connected to the first node, and a second gate electrode electrically connected to the first node; and

a first capacitor receiving the first voltage and electrically connected to the first node.

18. The display panel of claim 17, wherein the electrostatic discharging circuit further includes:

a third transistor including a fifth electrode receiving a second voltage, a sixth electrode electrically connected to the signal line, and a third gate electrode electrically connected to a second node;

a fourth transistor including a seventh electrode receiving the second voltage, an eighth electrode electrically connected to the second node, and a fourth gate electrode electrically connected to the second node; and

a second capacitor receiving the second voltage and electrically connected to the second node.

19. A display device comprising:

a display panel including a pixel, a first pad, and a signal line electrically connecting the pixel and the first pad;

a driving integrated circuit configured to receive a driving control signal through a second pad and configured to provide the display panel with a gate signal or a data signal;

a timing controller configured to generate the driving control signal; and

an electrostatic discharging circuit disposed adjacent to the first pad or the second pad,

wherein the electrostatic discharging circuit includes;

a first transistor including a first electrode electrically connected to the first pad or the second pad, a second electrode receiving a first voltage, and a first gate electrode electrically connected to a first node;

a second transistor including a third electrode electrically connected to the first pad or the second pad, a fourth electrode electrically connected to the first node, and a second gate electrode electrically connected to the first node; and

a first capacitor receiving the first voltage and electrically connected to the first node.

20. The display panel of claim 19, wherein the electrostatic discharging circuit further includes:

a third transistor including a fifth electrode receiving a second voltage, a sixth electrode electrically connected to the first pad or the second pad, and a third gate electrode electrically connected to a second node;

a fourth transistor including a seventh electrode receiving the second voltage, an eighth electrode electrically connected to the second node, and a third gate electrode electrically connected to the second node; and

a second capacitor receiving the second voltage and electrically connected to the second node.