EPITAXIAL GROWTH METHODS AND STRUCTURES THEREOF

• US 20170221709A1
• Filed: 04/01/2016
• Published: 08/03/2017
• Est. Priority Date: 01/29/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ueno, Tetsuji, Yu, Ming-Hua, Yang, Chan-Lon
• Granted Patent: US 10,453,925 B2
• Time in Patent Office: Days
• CPC Class Codes: C23C 16/0218 in a reactive atmosphere C23C16/0227 takes precedence
• CPC Class Codes: C23C 16/4408 by purging residual gases from the reaction chamber or gas lines
• CPC Class Codes: C30B 25/186 being specially pre-treated by, e.g. chemical or physical means
• CPC Class Codes: C30B 29/06 Silicon
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02576 N-type
• CPC Class Codes: H01L 21/02579 P-type
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02661 In-situ cleaning
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66568 Lateral single gate silicon transistors
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method and structure for providing a two-step defect reduction bake, followed by a high-temperature epitaxial layer growth. In various embodiments, a semiconductor wafer is loaded into a processing chamber. While the semiconductor wafer is loaded within the processing chamber, a first pre-epitaxial layer deposition baking process is performed at a first pressure and first temperature. In some cases, after the first pre-epitaxial layer deposition baking process, a second pre-epitaxial layer deposition baking process is then performed at a second pressure and second temperature. In some embodiments, the second pressure is different than the first pressure. By way of example, after the second pre-epitaxial layer deposition baking process and while at a growth temperature, a precursor gas may then be introduced into the processing chamber to deposit an epitaxial layer over the semiconductor wafer.

Claims

1. A method of semiconductor device fabrication, comprising:

loading a semiconductor wafer into a processing chamber;

while the semiconductor wafer is loaded within the processing chamber, performing a first pre-epitaxial layer deposition baking process at a first pressure and first temperature;

after the first pre-epitaxial layer deposition baking process, performing a second pre-epitaxial layer deposition baking process at a second pressure and second temperature, wherein the second pressure is different than the first pressure; and

after the second pre-epitaxial layer deposition baking process, introducing, while at a growth temperature, a precursor gas into the processing chamber to deposit an epitaxial layer over the semiconductor wafer.

3. The method of claim 1, wherein the first pressure is greater than about 500 Pa, and wherein the second pressure is less than about 100 Pa.

4. The method of claim 1, wherein the first temperature, the second temperature, and the growth temperature are each between about 700 C and about 800 C.

5. The method of claim 1, further comprising performing each of the first and second pre-epitaxial layer deposition baking processes for a duration greater than about 1 minute.

6. The method of claim 1, further comprising performing each of the first and second pre-epitaxial layer deposition baking processes in a hydrogen gas (H₂) ambient.

7. The method of claim 1, wherein the epitaxial layer is deposited at a growth pressure from about 10 Pa to about 100 Pa.

8. The method of claim 1, wherein the precursor gas includes a combination of a Si-based gas, a Cl-based gas, and a hydrogen gas (H₂).

9. The method of claim 8, wherein the Si-based gas includes silane (SiH₄), and wherein the Cl-based gas includes hydrogen chloride (HCl) gas.

10. The method of claim 9, wherein a flow rate of the hydrogen chloride (HCl) gas is about 200 sccm.

11. The method of claim 1, further comprising:

prior to performing the first pre-epitaxial layer deposition baking processes, performing a gas purge of the processing chamber and ramping a processing chamber temperature up to a processing temperature.

12. The method of claim 1, further comprising:

after the epitaxial layer is deposited, performing a gas purge of the processing chamber and ramping a processing chamber temperature down to room temperature.

2. The method of claim 2, wherein the epitaxial layer includes a silicon epitaxial layer.

13. A method of semiconductor device fabrication, comprising:

prior to deposition of an epitaxial layer, performing a two-step baking process of a semiconductor wafer within a processing chamber; and

after the performing the two-step baking process, depositing the epitaxial layer over the semiconductor wafer;

wherein the two-step baking process includes a first baking step performed at a first pressure and a second baking step performed at a second pressure different than the first pressure, and wherein the first baking step removes a first contaminant and the second baking step removes a second contaminant.

14. The method of claim 13, wherein the first pressure is about 1000 Pa, and wherein the second pressure is about 20 Pa.

15. The method of claim 13, wherein the first contaminant includes oxygen, and wherein the second contaminant includes carbon.

16. The method of claim 13, wherein each of the first and second baking steps are performed for a duration of about 1 hour.

17. The method of claim 13, wherein each of the first and second baking steps are performed at a temperature of about 800 C.

18. The method of claim 13, wherein the depositing the epitaxial layer further includes simultaneously flowing, while at a growth temperature, silane (SiH₄) and hydrogen chloride (HCl) gas into the processing chamber.

19. A method of semiconductor device fabrication, comprising:

loading a semiconductor wafer into a processing chamber;

performing a first purge of the processing chamber and ramping a processing chamber temperature up to a first baking temperature;

after the first purge, performing a first baking process in a hydrogen gas (H₂) ambient at a first baking pressure and at the first baking temperature, wherein the first baking process removes carbon contamination;

subsequent to the first baking process, performing a second baking process in the hydrogen gas (H₂) ambient at a second baking pressure and at a second baking temperature, wherein the second baking pressure is less than the first baking pressure, and wherein the second baking process removes oxygen contamination;

after the second baking process, depositing an epitaxial layer over the semiconductor wafer by flowing silane (SiH₄) and hydrogen chloride (HCl) gas over the semiconductor wafer at a growth pressure and at a growth temperature; and

following the depositing the epitaxial layer, performing a second purge of the processing chamber and ramping the processing chamber temperature down to room temperature.

20. The method of claim 19, wherein the first pressure is about 1000 Pa, and wherein the second pressure is about 20 Pa.