METHOD OF FABRICATING FIN FIELD EFFECT TRANSISTOR

• US 20170222026A1
• Filed: 02/03/2016
• Published: 08/03/2017
• Est. Priority Date: 02/03/2016
• Status: Abandoned Application

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Lin, Chun-Hao, Chen, Yi-Ren, Hsieh, Shou-Wei, Chuang, Yuan-Ting, Liu, Che-Hung, Chen, Hsin-Yu
• Application Number:
  US15/014,037
• Publication Number:
  US 20170222026A1
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7847 using a memorization technique, e.g. re-crystallization under strain, bonding on a substrate having a thermal expansion coefficient different from the one of the region

Abstract

The present invention provides a method of fabricating a fin field effect transistor (finFET), comprising: firstly, an interfacial layer is formed on a fin structure, next, a high-k dielectric layer is formed on the interfacial layer; afterwards, a stress film is formed on the high-k dielectric layer, an annealing process is then performed to the stress film, and an etching process is performed to remove the stress film.

Claims

1. A method of fabricating a fin field effect transistor (finFET), comprising:

forming an interfacial layer on a fin structure;

forming a high-k dielectric layer on the interfacial layer;

forming a stress film on the high-k dielectric layer;

performing an annealing process on the stress film; and

performing an etching process to remove the stress film.

2. The method of claim 1, wherein the stress film comprises a silicon nitride layer or a silicon carbonitride (SiCN) layer.

3. The method of claim 1, wherein stress film does not comprise a metal nitride layer.

4. The method of claim 1, wherein the stress film does not comprise a polysilicon layer.

5. The method of claim 1, wherein the high-k layer is not removed after the etching process for removing the stress film is performed.

6. The method of claim 5, wherein the etching process comprises a Standard Clean 1 (SC1) process.

7. The method of claim 1, wherein the etching process does not comprise a dilute hydrofluoric acid containing cleaning process.

8. The method of claim 1, further comprising forming a bottom barrier layer (BBM) after the stress film is removed.

9. The method of claim 8, wherein the bottom barrier layer comprises a tantalum nitride (TaN) layer.

10. The method of claim 9, wherein the BBM directly contacts the high-k dielectric layer.

11. The method of claim 8, wherein the BBM does not comprise a titanium nitride (TiN) layer.

12. The method of claim 1, wherein the anneal process is performed with a N₂ plasma.

13. The method of claim 12, wherein the temperature of the anneal process is between 400°

C. and 900°

C.

14. The method of claim 1, wherein the anneal process is performed without a N₂ plasma.

15. The method of claim 14, wherein the temperature of the anneal process is higher than 1000°

C.

16. The method of claim 1, further comprising forming a metal gate in the gate trench.

17. The method of claim 1, further comprising forming an ILD on a substrate, and a dummy gate is disposed in the ILD, wherein the dummy gate covers a portion of the fin structure.

18. The method of claim 7, further comprising removing the dummy gate to form the gate trench.