SOI POWER LDMOS DEVICE
First Claim
1. A laterally diffused metal oxide semiconductor (LDMOS) device, comprising:
- a handle portion having a blanket buried dielectric (BOX) layer thereon and a semiconductor layer on said BOX layer, said semiconductor layer doped a second dopant type;
a drift region doped a first dopant type within said semiconductor layer to provide a drain extension region;
a gate stack including a gate dielectric layer over a channel portion of said semiconductor layer adjacent to and on respective sides of a junction with said drift region and a patterned gate electrode on said gate dielectric layer;
a DWELL region within said semiconductor layer;
a source region doped said first dopant type within said DWELL region;
a drain region doped said first dopant type within said drift region;
a first partial buried layer doped said second dopant type in a first portion of said drift region including under at least a portion of said gate electrode, anda second partial buried layer doped said first dopant type in a second portion of said drift region including under said drain region.
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Accused Products
Abstract
An LDMOS device includes a handle portion having a buried dielectric layer and a semiconductor layer thereon doped a second dopant type. A drift region doped a first type is within the semiconductor layer providing a drain extension. A gate stack includes a gate electrode on a gate dielectric layer on respective sides of a junction with the drift region. A DWELL region is within the semiconductor layer. A source region doped the first type is within the DWELL region. A drain region doped the first type is within the drift region. A first partial buried layer doped the second type is in a first portion of the drift region including under the gate electrode. A second partial buried layer doped the first type is in a second portion of the drift region including under the drain.
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Citations
18 Claims
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1. A laterally diffused metal oxide semiconductor (LDMOS) device, comprising:
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a handle portion having a blanket buried dielectric (BOX) layer thereon and a semiconductor layer on said BOX layer, said semiconductor layer doped a second dopant type; a drift region doped a first dopant type within said semiconductor layer to provide a drain extension region; a gate stack including a gate dielectric layer over a channel portion of said semiconductor layer adjacent to and on respective sides of a junction with said drift region and a patterned gate electrode on said gate dielectric layer; a DWELL region within said semiconductor layer; a source region doped said first dopant type within said DWELL region; a drain region doped said first dopant type within said drift region; a first partial buried layer doped said second dopant type in a first portion of said drift region including under at least a portion of said gate electrode, and a second partial buried layer doped said first dopant type in a second portion of said drift region including under said drain region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method of forming a laterally diffused metal oxide semiconductor (LDMOS) device, comprising:
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providing a handle portion having a blanket buried dielectric (BOX) layer thereon and a semiconductor layer on said BOX layer, said semiconductor layer doped a second dopant type; forming a first partial buried layer doped said second dopant type in a first portion of said semiconductor layer; forming a second partial buried layer doped a first dopant type in a second portion of said semiconductor layer; forming a drift region doped said first dopant type within said semiconductor layer; implanting a portion of said semiconductor layer lateral to said drift region including at least a first well implant comprising said second dopant type (DWELL implant) into said semiconductor layer to form a DWELL region; forming a gate stack including forming a gate dielectric layer over a channel region in said semiconductor layer adjacent to and on respective sides of a junction with said drift region, then a patterned gate electrode on said gate dielectric layer, wherein said gate stack is formed at least in part over said first partial buried layer; forming a source region within said DWELL region, and forming a drain region within said drift region and over said second partial buried layer. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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Specification