OPTOELECTRONIC SEMICONDUCTOR CHIP AND METHOD OF PRODUCING THE SAME

• US 20170222088A1
• Filed: 09/22/2015
• Published: 08/03/2017
• Est. Priority Date: 09/30/2014
• Status: Active Grant

• Current Assignee: OSRAM OLED GMBH (Ams-Osram AG)
• Original Assignee: Osram Opto Semiconductors GmbH (Ams-Osram AG)
• Inventors: Klemp, Christoph
• Granted Patent: US 10,490,698 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/14 with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01L 33/405 Reflective materials
• CPC Class Codes: H01L 33/46 Reflective coating, e.g. dielectric Bragg reflector

Abstract

An optoelectronic semiconductor chip includes a semiconductor layer sequence and a carrier substrate, wherein the semiconductor layer sequence includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type and an active layer arranged between the first semiconductor region and the second semiconductor region, wherein the first semiconductor region faces the carrier substrate, the semiconductor layer sequence includes first recesses formed in the first semiconductor region and that do not separate the active layer, the semiconductor layer sequence includes second recesses that at least partially separate the first semiconductor region and the active layer, and the second recesses adjoin a first recess or are arranged between two first recesses.

Claims

1-15. -15. (canceled)

16. An optoelectronic semiconductor chip comprising a semiconductor layer sequence and a carrier substrate, wherein

the semiconductor layer sequence comprises a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type and an active layer arranged between the first semiconductor region and the second semiconductor region, wherein the first semiconductor region faces the carrier substrate,

the semiconductor layer sequence comprises first recesses formed in the first semiconductor region and that do not separate the active layer,

the semiconductor layer sequence comprises second recesses that at least partially separate the first semiconductor region and the active layer, and

the second recesses adjoin a first recess or are arranged between two first recesses.

17. The optoelectronic semiconductor chip according to claim 16, wherein the first recesses and/or the second recesses have a depth of 0.1 μ

m to 10 μ

m.

18. The optoelectronic semiconductor chip according to claim 16, wherein the first recesses and/or the second recesses comprise oblique side surfaces.

19. The optoelectronic semiconductor chip according to claim 16, wherein the first recesses and/or the second recesses have a cross-sectional area that decreases from the carrier substrate.

20. The optoelectronic semiconductor chip according to claim 16, wherein the first recesses and/or the second recesses have a trapezoidal cross-sectional area.

21. The optoelectronic semiconductor chip according to claim 16, wherein the first recesses and/or the second recesses are prism-shaped.

22. The optoelectronic semiconductor chip according to claim 16, wherein the first recesses have a greater width than the second recesses, and the second recesses adjoin a first recess when viewed from the carrier substrate in each case in a vertical direction.

23. The optoelectronic semiconductor chip according to claim 16, wherein the first recesses have a width of 20 μ

m to 50 μ

m and the second recesses have a width of 2 μ

m to 20 μ

m.

24. The optoelectronic semiconductor chip according to claim 16, wherein the width of the first recesses is greater than a width of the second recesses by at least 10 μ

m.

25. The optoelectronic semiconductor chip according to claim 16, wherein the second recesses do not adjoin the first recesses and are arranged to be centered between two first recesses in a lateral direction.

26. The optoelectronic semiconductor chip according to claim 25, wherein the first recesses have a lateral distance of at least 20 μ

m and 50 μ

m at the most, and the second recesses have a width of 2 μ

m to 20 μ

m.

27. A method of producing an optoelectronic semiconductor chip, comprising:

applying a semiconductor layer sequence to a growth substrate, wherein the semiconductor layer sequence comprises a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type and an active layer arranged between the first semiconductor region and the second semiconductor region, wherein the second semiconductor region faces the growth substrate,

forming first recesses in the first semiconductor region by a first etching process, wherein the first recesses do not separate the active layer,

forming second recesses that separate the active layer by a second etching process, wherein the second recesses adjoin a first recess or are arranged between two first recesses, and wherein the first recesses and the second recesses comprise oblique side surfaces,

connecting the semiconductor layer sequence with a carrier substrate such that the recesses face the carrier substrate, and

removing the growth substrate.

28. The method according to claim 27, wherein, in the second etching process, the second recesses are each generated in the center of a first recess, and the first recesses are wider than the second recesses.

29. The method according to claim 27, wherein, in the second etching process, the second recesses are each produced in the center between two first recesses.

30. The method according to claim 29, wherein the first recesses neighboring a second recess are spaced from the second recess by no more than 25 μ

m in the lateral direction.

31. The method according to claim 27, wherein regions of a first main surface of the semiconductor layer sequence that are arranged between a second recess and a neighboring first recess, are not electrically contacted.

32. An optoelectronic semiconductor chip comprising a semiconductor layer sequence and a carrier substrate, wherein

the semiconductor layer sequence comprises a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type and an active layer arranged between the first semiconductor region and the second semiconductor region, wherein the first semiconductor region faces the carrier substrate,

the semiconductor layer sequence comprises first recesses formed in the first semiconductor region and that do not separate the active layer,

the semiconductor layer sequence comprises second recesses that at least partially separate the first semiconductor region and the active layer,

the second recesses adjoin a first recess or are arranged between two first recesses, and

the first recesses and the second recesses comprise oblique side surfaces.

33. The optoelectronic semiconductor chip according to claim 32, wherein regions of a first main surface of the semiconductor layer sequence arranged between a second recess and a neighboring first recess are not electrically contacted.