INTEGRATED CIRCUIT THAT CONTROLS A SEARCH SPACE SETTING PROCESS

• US 20170223683A1
• Filed: 04/13/2017
• Published: 08/03/2017
• Est. Priority Date: 10/31/2008
• Status: Active Grant

• Current Assignee: Godo Kaisha IP Bridge 1 (IP Bridge, Inc.)
• Original Assignee: Godo Kaisha IP Bridge 1 (IP Bridge, Inc.)
• Inventors: Nishio, Akihiko, Nakao, Seigo, Imamura, Daichi, Hoshino, Masayuki
• Granted Patent: US 9,854,579 B2
• Time in Patent Office: Days
• CPC Class Codes: H04L 1/0025 Transmission of mode-switching indication
• CPC Class Codes: H04L 1/0027 Scheduling of signalling, e.g. occurrence thereof
• CPC Class Codes: H04L 1/0038 Blind format detection for detection of modulation format H04L27/0012
• CPC Class Codes: H04L 1/0046 Code rate detection or code type detection H04L1/0038 takes precedence; detection of the data rate H04L25/0262; for packet format H04L1/0091
• CPC Class Codes: H04L 1/0072 Error control for data other than payload data, e.g. control data
• CPC Class Codes: H04L 1/1854 Scheduling and prioritising arrangements
• CPC Class Codes: H04L 1/1861 Physical mapping arrangements for ACK signaling see also H04L5/0053
• CPC Class Codes: H04L 5/001 the frequencies being arranged in component carriers
• CPC Class Codes: H04L 5/0042 intra-user or intra-terminal allocation
• CPC Class Codes: H04L 5/0044 allocation of payload
• CPC Class Codes: H04L 5/0053 Allocation of signaling, i.e. of overhead other than pilot signals
• CPC Class Codes: H04L 5/0055 Physical resource allocation for ACK/NACK for physical mapping arrangements in ARQ protocols H04L1/1861
• CPC Class Codes: H04L 5/0092 Indication of how the channel is divided
• CPC Class Codes: H04L 5/0094 Indication of how sub-channels of the path are allocated
• CPC Class Codes: H04W 28/04 Error control
• CPC Class Codes: H04W 72/0453 Resources in frequency domain, e.g. a carrier in FDMA
• CPC Class Codes: H04W 72/20 Control channels or signalling for resource management
• CPC Class Codes: H04W 72/21 in the uplink direction of a wireless link, i.e. towards the network
• CPC Class Codes: H04W 72/23 in the downlink direction of a wireless link, i.e. towards a terminal
• CPC Class Codes: H04W 72/29 between an access point and the access point controlling device
• CPC Class Codes: H04W 74/085 : collision avoidance
• CPC Class Codes: H05K 999/00 : dummy group
• CPC Class Codes: H05K 999/99 : dummy group

Abstract

An integrated circuit, for example, included in a wireless communication base station, controls a process that includes mapping a first downlink control channel to control channel element(s) (CCE(s)) in a first search space comprised of a first plurality of CCEs, the first downlink control channel including resource assignment information, which indicates a resource allocated to a terminal in a component carrier n (CC_n) out of one or more component carrier(s) (CC(s)), and mapping a second downlink control channel to CCE(s) in a second search space comprised of a second plurality of CCE(s), the second downlink control channel including resource assignment information, which indicates a resource allocated to the terminal in a component carrier n+1 (CC₊₁) out of the CC(s), the first plurality of CCEs and the second plurality of CCEs are consecutive. The process also includes transmitting the first and the second downlink control channels to the terminal.

Claims

1. An integrated circuit to control a process, the process comprising:

mapping a first downlink control channel to one or more control channel element(s) (CCE(s)) in a first search space that is comprised of a first plurality of CCEs, the first downlink control channel including resource assignment information, which indicates a resource allocated to a terminal in a component carrier n (CC_n) out of one or more component carrier(s) (CC(s)), and mapping a second downlink control channel to one or more CCE(s) in a second search space that is comprised of a second plurality of CCE(s), the second downlink control channel including resource assignment information, which indicates a resource allocated to the terminal in a component carrier n+1 (CC_n+1) out of said CC(s), the first plurality of CCEs and the second plurality of CCEs are consecutive; and

transmitting, to the terminal, the first downlink control channel and the second downlink control channel.

2. The integrated circuit according to claim 1, comprising:

circuitry which, in operation, controls the process;

at least one input coupled to the circuitry, wherein the at least one input, in operation, inputs data; and

at least one output coupled to the circuity, wherein the at least one output, in operation, outputs data.

3. The integrated circuit according to claim 1, wherein a number of the one or more CC(s) that are configured for downlink is greater than a number of the one or more CC(s) that are configured for uplink.

4. The integrated circuit according to claim 1, wherein at least one of the one or more CC(s) is configured for downlink and is also configured for uplink.

5. The integrated circuit according to claim 1, wherein the first search space and the second search space neighbor each other.

6. The integrated circuit according to claim 1, wherein a CCE number S_n+1, which defines a start position of the second search space, is set as (S_n+L) mod N_CCE, where a CCE number S_n defines a start position of the first search space, L is a number of the first plurality of CCEs, and N_CCE is a total number of CCEs within the CC_n.

7. The integrated circuit according to claim 1, wherein a difference between CCE numbers that respectively define start positions of the first search space and the second search space, varies among a plurality of terminals.

8. The integrated circuit according to claim 1, wherein the first search space and the second search space are set independently of each other.

9. The integrated circuit according to claim 1, the process comprising receiving multiple ACK/NACK signals, which are for the CC and the CC_n+1 and which are transmitted from the terminal in one of the CC and the CC_n+1.

10. The integrated circuit according to claim 1, wherein the first plurality of CCEs and the second plurality of CCEs correspond to downlink control channel candidates to be decoded by the terminal.

11. The integrated circuit according to claim 1, wherein each of the first search space and the second search space is comprised of a plurality of CCEs having consecutive CCE numbers.

12. An integrated circuit comprising

circuitry, which, in operation:

maps a first downlink control channel to one or more control channel element(s) (CCE(s)) in a first search space that is comprised of a first plurality of CCEs, the first downlink control channel including resource assignment information, which indicates a resource allocated to a terminal in a component carrier n (CC_n) out of one or more component carrier(s) (CC(s)), and maps a second downlink control channel to one or more CCE(s) in a second search space that is comprised of a second plurality of CCE(s), the second downlink control channel including resource assignment information, which indicates a resource allocated to the terminal in a component carrier n+1 (CC₊₁) out of said CC(s), the first plurality of CCEs and the second plurality of CCEs are consecutive; and

controls transmission, to the terminal, of the first downlink control channel and the second downlink control channel.

13. The integrated circuit according to claim 12, comprising:

at least one input coupled to the circuitry, wherein the at least one input, in operation, inputs data; and

at least one output coupled to the circuity, wherein the at least one output, in operation, outputs data.

14. The integrated circuit according to claim 12, wherein a number of the one or more CC(s) that are configured for downlink is greater than a number of the one or more CC(s) that are configured for uplink.

15. The integrated circuit according to claim 12, wherein at least one of the one or more CC(s) is configured for downlink and is also configured for uplink.

16. The integrated circuit according to claim 12, wherein the first search space and the second search space neighbor each other.

17. The integrated circuit according to claim 12, wherein a CCE number S_n+1, which defines a start position of the second search space, is set as (S_n+L) mod N_CCE, where a CCE number S_n defines a start position of the first search space, L is a number of the first plurality of CCEs, and N_CCE is a total number of CCEs within the CC_n.

18. The integrated circuit according to claim 12, wherein a difference between CCE numbers that respectively define start positions of the first search space and the second search space, varies among a plurality of terminals.

19. The integrated circuit according to claim 12, wherein the first search space and the second search space are set independently of each other.

20. The integrated circuit according to claim 12, wherein the circuitry, in operation, controls reception of multiple ACK/NACK signals, which are for the CC and the CC_n+1 and which are transmitted from the terminal in one of the CC and the CC_n+1.

21. The integrated circuit according to claim 12, wherein the first plurality of CCEs and the second plurality of CCEs correspond to downlink control channel candidates to be decoded by the terminal.

22. The integrated circuit according to claim 12, wherein each of the first search space and the second search space is comprised of a plurality of CCEs having consecutive CCE numbers.