METHOD AND APPARATUS FOR UPDATING A SYSTEM ON CHIP (SOC) IMAGE FROM A HOST COMPUTER SYSTEM WITHOUT USING DMA

• US 20170228302A1
• Filed: 02/10/2016
• Published: 08/10/2017
• Est. Priority Date: 02/10/2016
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: HGST Netherlands B.V. (Western Digital Corporation)
• Inventors: Devireddy, Kishore Kumar Reddy, Chiang, Chuck
• Granted Patent: US 9,934,120 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/0709 in a distributed system consisting of a plurality of standalone computer nodes, e.g. clusters, client-server systems
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06
• CPC Class Codes: G06F 11/079 Root cause analysis, i.e. error or fault diagnosis in a hardware test environment G06F11/22; in a software test environment G06F11/36
• CPC Class Codes: G06F 11/1433 during software upgrading
• CPC Class Codes: G06F 11/3041 where the computing system component is an input/output interface interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units G06F13/00
• CPC Class Codes: G06F 11/3055 Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available error or fault processing without redundancy G06F11/0703; error detection or correction by redundancy in data representation G06F11/08; error detection or correction by redundancy in operation G06F11/14; error detection or correction by redundancy in hardware G06F11/16
• CPC Class Codes: G06F 11/327 Alarm or error message display
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

Embodiments of the present disclosure relate to systems and methods for updating a System on Chip (SOC) image without using direct memory access (DMA) programming. A target SOC monitors a target mailbox to determine reception of a data packet of an SOC image received from a host computer, wherein the SOC image includes a plurality of data packets. The target SOC reads the data packet from a buffer of the target SOC and writes a status message to a host mailbox of the target SOC, wherein the status message is indicative of a reception status of the data packet.

Claims

1. A method for updating a system on chip (SOC) image operable at a target SOC, the method comprising:

monitoring a target mailbox of the target SOC to determine reception of a data packet of an SOC image received from a host computer, wherein the SOC image comprises a plurality of data packets;

reading the data packet from a buffer of the target SOC; and

writing a status message to a host mailbox of the target SOC, wherein the status message is indicative of a reception status of the data packet.

2. The method of claim 1,

wherein the monitoring the target mailbox comprises monitoring a status bit associated with the target mailbox, and

wherein the status bit is indicative of an availability of the data packet in the buffer.

3. The method of claim 2, further comprising:

clearing the status bit in connection with reading the data packet from the buffer.

4. The method of claim 1,

wherein the monitoring the target mailbox comprises monitoring an error bit associated with the target mailbox, and

wherein the error bit is indicative of an error in the data packet in the buffer.

5. The method of claim 4, further comprising setting the error bit when the target mailbox is written at least twice consecutively by the host computer.

6. The method of claim 1, further comprising:

reading a sequence number of the data packet from the target mailbox; and

if the sequence number indicates the data packet is a last one of the plurality of data packets, updating the target SOC with a received SOC image comprising at least the data packet.

7. The method of claim 1, wherein the writing the status message to the host mailbox comprises:

if an error bit associated with the target mailbox is set, writing a first value to the host mailbox indicative of an error in receiving the data packet; and

if the error bit associated with the target mailbox is not set, writing a second value to the host mailbox indicative of a success in receiving the data packet.

8. A method for operating a host computer to update a system on chip (SOC) image of a target SOC, the method comprising:

copying a first data packet of an SOC image to a buffer of the target SOC, wherein the SOC image comprises a plurality of data packets;

writing a first sequence number of the first data packet to a target mailbox of the target SOC; and

receiving a status message from the target SOC, wherein the status message is indicative of a reception status of the first data packet.

9. The method of claim 8, wherein the receiving the status message comprises reading the status message from a host mailbox of the target SOC.

10. The method of claim 8, further comprising:

if the status message indicates a reception error, writing the first data packet to the buffer for a second time.

11. The method of claim 8, further comprising:

if the status message indicates no reception error;

writing a second data packet of the plurality of packets to the buffer; and

writing a second sequence number of the second data packet to the target mailbox.

12. The method of claim 8, wherein the copying the first data packet involves no direct memory access (DMA).

13. A system on chip (SOC) system comprising:

a processor;

a buffer coupled to the processor and configured to receive a data packet of an SOC image from a host computer via a communication interface, wherein the SOC image comprises a plurality of data packets;

a target mailbox coupled to the processor and configured to receive a message from the host computer, wherein the message comprises a sequence number of the data packet received in the buffer; and

a host mailbox coupled to the processor and configured to provide a status message to the host computer,

wherein the status message is indicative of a reception status of the data packet.

14. The SOC system of claim 13, further comprising:

a status bit associated with the target mailbox, wherein the status bit is indicative of an availability of the data packet in the buffer.

15. The SOC system of claim 14, wherein the status bit is configured to be cleared when the data packet is read from the buffer.

16. The SOC system of claim 13, further comprising:

an error bit associated with the target mailbox, wherein the error bit is indicative of an error in the data packet in the buffer.

17. The SOC system of claim 16, wherein the error bit is configured to be set when the target mailbox being written at least twice consecutively by the host computer.

18. The SOC system of claim 13, further comprising:

a flash memory comprising an image file,

wherein if the sequence number indicates the received data packet is a last one of the plurality of data packets, the processor is configured to update the image file with a received SOC image comprising at least the data packet.

19. The SOC system of claim 13, further comprising:

an error bit associated with the target mailbox,

wherein the processor is configured to;

if the error bit is set, write a first value to the host mailbox indicative of an error in receiving the data packet; and

if the error bit is not set, write a second value to the host mailbox indicative of a success in receiving the data packet.

20. A host computer configured to update a system on chip (SOC) image of a target SOC, comprising:

a processor;

a communication interference configured to communicate with a target SOC; and

a memory coupled to the processor and comprising an SOC update application,

wherein the processor, when executing the SOC update application, is configured to;

copy a first data packet of an SOC image to a buffer of a target SOC, wherein the SOC image comprises a plurality of data packets;

write a first sequence number of the first data packet to a target mailbox of the target SOC; and

receive a status message from the target SOC, wherein the status message is indicative of a reception status of the first data packet.

21. The host computer of claim 20, wherein the processor is further configured to read the status message from a host mailbox of the target SOC.

22. The host computer of claim 20, wherein the processor is further configured to:

if the status message indicates a reception error, write the first data packet to the buffer for a second time.

23. The host computer of claim 20, wherein the processor is further configured to:

if the status message indicates no reception error;

write a second data packet of the plurality of packets to the buffer; and

write a second sequence number of the second data packet to the target mailbox.