INTEGRATED PASSIVE DEVICE PACKAGE AND METHODS OF FORMING SAME

• US 20170229322A1
• Filed: 08/01/2016
• Published: 08/10/2017
• Est. Priority Date: 02/10/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hsu, Feng-Cheng, Chen, Shuo-Mao, Hung, Jui-Pin, Jeng, Shin-Puu
• Granted Patent: US 9,911,629 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/02373 Layout of the redistribution layers
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/81005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/83 : using a layer connector
• CPC Class Codes: H01L 2224/92244 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/5383 : Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/00 : Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/00 : Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereofdevices consisting of a plurality of solid state components formed in or on a common substrate H01L27/00; photovoltaic modules or arrays of photovoltaic cells H01L31/042 ; panels or arrays of photo electrochemical cells H01G9/2068
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA

Abstract

An embodiment device package includes a first die, a second die, and a molding compound extending along sidewalls of the first die and the second die. The package further includes redistribution layers (RDLs) extending laterally past edges of the first die and the second die. The RDLs include an input/output (I/O) contact electrically connected to the first die and the second die, and the I/O contact is exposed at a sidewall of the device package substantially perpendicular to a surface of the molding compound opposite the RDLs.

Claims

1. A device package comprising:

a first die;

a second die;

a molding compound extending along sidewalls of the first die and the second die; and

redistribution layers (RDLs) extending laterally past edges of the first die and the second die, wherein the RDLs comprise an input/output (I/O) contact electrically connected to the first die and the second die, wherein a portion of the I/O contact is exposed at a sidewall of the device package, and wherein a solder region contacts the portion of the I/O contact exposed at the sidewall of the device package.

2. The device package of claim 1, wherein the first die is an integrated passive device die substantially free of any transistors or diodes.

3. The device package of claim 1, wherein the second die comprises a transistor, a diode, or a combination thereof.

4. The device package of claim 1, wherein the I/O contact extends to a surface of the molding compound opposite the RDLs.

5. The device package of claim 1, wherein the second die is adjacent the first die.

6. The device package of claim 1, wherein the second die is disposed on an opposing side of the RDLs as the first die.

7. The device package of claim 1, wherein the RDLs further comprises one or more layers of conductive lines electrically connecting the first die and the second die to the I/O contact.

8. A package comprising:

a substrate;

a solder region over the substrate; and

a first device package bonded to the substrate by the solder region, wherein the first device package comprises;

a plurality of passive device dies;

a first molding compound encapsulating at least one of the plurality of passive device dies, wherein all dies encapsulated by the first molding compound is substantially free of any active regions; and

first redistribution layers (RDLs) extending laterally past edges of the plurality of passive device dies, wherein the first RDLs electrically connects the plurality of passive device dies to the substrate.

9. The package of claim 8, wherein the first RDLs comprises a first input/output (I/O) contact exposed at a sidewall of the first device package, and wherein the solder region contacts the first I/O contact at the sidewall of the first device package.

10. The package of claim 9, wherein the first I/O contact comprises a first surface substantially level with a second surface of the first molding compound opposite the first RDLs.

11. The package of claim 10, wherein the solder region further contacts the first surface of the first I/O contact.

12. The package of claim 10 further comprising a second device package over the first device package and bonded to the substrate, wherein the second device package comprises:

a plurality of additional device dies;

a second molding compound encapsulating at least one of the plurality of additional device dies; and

second RDLs electrically connected to and extending laterally past edges of the plurality of additional device dies, wherein the second RDLs comprises a second I/O contact exposed at a sidewall of the second device package, and wherein a line perpendicular to the first surface of the first I/O contact intersects the second I/O contact.

13. The package of claim 12, wherein the first I/O contact contacts the second I/O contact.

14. The package of claim 8, wherein a first one of the plurality of passive device dies is disposed on an opposing side of the first RDLs as a second one of the plurality of passive device dies.

15. The package of claim 8 further comprising:

third RDLs disposed on an opposing side of the first molding compound as the first RDLs; and

a conductive via extending through the first molding compound and electrically connecting the third RDLs to the first RDLs.

16. A method comprising:

forming redistribution layers (RDLs) over a carrier substrate;

bonding a first die and a second die to the RDLs;

encapsulating the first die and the second die in a molding compound;

removing the carrier substrate; and

singulating the first die from the second die along a scribe line, wherein the scribe line extends through a conductive feature in the RDLs.

17. The method of claim 16, wherein singulating the first die from the second die comprises using a singulation process in accordance with a thickness of the conductive feature.

18. The method of claim 17, wherein the singulation process comprises mechanical dicing, laser grooving, water-assisted laser cutting, routing machining, or a combination thereof.

19. The method of claim 16 further comprising planarizing the molding compound to expose a surface of the conductive feature.

20. The method of claim 16 further comprising attaching a third die to the carrier substrate, wherein forming the RDLs comprises forming the RDLs over the third die, and wherein bonding the first die and the second die comprises bonding the first die and the second die to an opposing surface of the RDLs as the third die.