SEMICONDUCTOR INTEGRATED CIRCUIT

• US 20170229457A1
• Filed: 08/25/2016
• Published: 08/10/2017
• Est. Priority Date: 02/04/2016
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: MAENO, Muneaki
• Granted Patent: US 10,453,840 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0738 in combination with resistors only
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors

Abstract

A semiconductor integrated circuit comprises first and second transistors, and a resistive element. The first transistor includes first and second regions of first conductivity type in a first well region of opposite conductivity type, and a first gate electrode on the first well region between the first and second regions. The second transistor includes third and fourth region of second conductivity type in a second well region of opposite conductivity type, and a second gate electrode on the second well region between the third and fourth regions. The first region is connected to a first line, and the third and fourth regions are connected to a second line. The resistance element includes a first end connected to the first and second gate electrodes, a second end connected to the second line, and a resistive electrical path between the first and second ends including a portion of the third region.

Claims

1. A semiconductor integrated circuit, comprising:

a first transistor comprising a first impurity region of a first conductivity type in a first well region of a conductivity type opposite the first conductivity type, a second impurity region of the first conductivity type in the first well, and a first gate electrode on the first well region between the first and second impurity regions, the first impurity region being electrically connected to a first power line;

a second transistor comprising a third impurity region of a second conductivity type in a second well region of a conductivity type opposite the second conductivity type, a fourth impurity region of the second conductivity type in the second well, a second gate electrode on the second well region between the third and fourth impurity regions, the second gate electrode being electrically connected to the first gate electrode, and the third and fourth impurity regions being electrically connected to a second power line; and

a resistance element comprising a first end electrically connected to the first and second gate electrodes, a second end electrically connected to the second power line, and a resistive electrical path between the first and second ends including a portion of the third impurity region.

2. The semiconductor integrated circuit according to claim 1, wherein the first transistor is a PMOS transistor, and the second transistor is an NMOS transistor.

3. The semiconductor integrated circuit according to claim 1, wherein the first transistor is an NMOS transistor, and the second transistor is a PMOS transistor.

4. The semiconductor integrated circuit according to claim 1, wherein the first conductivity type is p type, and the second conductivity is n type.

5. The semiconductor integrated circuit according to claim 1, wherein the first gate electrode and the second gate electrode are a single, continuous wire disposed on a gate insulating film and extending from the first well region to the second well region.

6. The semiconductor integrated circuit according to claim 1, wherein

the first power line and the second power line are disposed in a wiring level above a gate level in which the first and second gate electrodes are disposed,

an electrical connection between the first impurity region and first power line is through a first via,

an electrical connection between the third impurity region and the second power line is through a second via,

an electrical connection between the first end of the resistance element and the first and second gate electrodes is through a third via disposed on the third impurity region, a wiring connection portion connected to the third via and disposed in the wiring level, and fourth via disposed on at least one of the first and second gate electrodes.

7. The semiconductor integrated circuit according to claim 1, further comprising:

a third transistor comprising a fifth impurity region of the first conductivity type in the first well region, the second impurity region, and a third gate electrode on the first well region between the second impurity region and the fifth impurity region, the second and fifth impurity regions being electrically connected to the first power line, the third gate electrode being electrically connected to the first gate electrode; and

a fourth transistor comprising a sixth impurity region of the second conductivity type in the second well region, the third impurity region, and a fourth gate electrode on the second well region between the third and sixth impurity regions, the fourth gate electrode being electrically connected to the second gate electrode.

8. The semiconductor integrated circuit according to claim 7, wherein the first and third transistors are PMOS transistors, and the second and fourth transistors are NMOS transistors.

9. The semiconductor integrated circuit according to claim 7, wherein the first and third transistors are NMOS transistors, and the second and fourth transistors are PMOS transistors.

10. A semiconductor integrated circuit, comprising:

a first well region and a second well region on a surface of a substrate;

a first impurity region and a second impurity region on a surface of the first well region, the first and second impurity regions having a first conductivity type that is opposite a conductivity type of the first well region;

a third impurity region and a fourth impurity region on a surface of the second well region, the second and third impurity regions having a second conductivity type that is opposite a conductivity type of the second well region;

a first wiring layer on the first well region between the first and second impurity regions and on the second well region between the third and fourth impurity regions;

a first via and a second via contacting a surface of the third impurity region, the first and second vias spaced from each other on the surface of the third impurity region;

a third via contacting the first wiring layer;

a second wiring layer connecting the first via to the third via; and

a third wiring layer contacting the second via and electrically connected to the second wiring layer through a portion of the third impurity region between the first and second vias, wherein

the first and second impurity regions are a source or a drain region of a first transistor having a first gate electrode formed by a first portion of the first wiring layer, the third and fourth impurity regions are a source or drain region of a second transistor having a second gate electrode formed by a second portion of the first wiring layer, and

the first and second gate electrodes are connected in common to each other.

11. The semiconductor integrated circuit according to claim 10, wherein

the first impurity region is connected to a first power line,

the third and fourth impurity regions are connected to a second power line, and

the first and second gate electrodes are connected to the second power line only through an electrical path including the portion of the third impurity region.

12. The semiconductor integrated circuit according to claim 11, wherein the first transistor is a PMOS transistor, and the second transistor is a NMOS transistor.

13. The semiconductor integrated circuit according to claim 11, wherein the first, second, third, and fourth impurity regions are formed by an impurity diffusion method.

14. The semiconductor integrated circuit according to claim 11, wherein

the first wiring layer is polysilicon, and

the second and third wiring layers are metal.

15. The semiconductor integrated circuit according to claim 11, wherein the second and third wiring layers are at a same distance from the surface of the substrate in a direction orthogonal to the surface of the substrate.

16. The semiconductor integrated circuit according to claim 11, further comprising:

a fifth impurity region of the first conductivity type on the surface of the first well region;

a fourth wiring layer on the surface of the first well region between the second impurity region and the fifth impurity region, the second and fifth impurity regions being electrically connected to a first power line, the fourth wiring layer being electrically connected to the first wiring layer;

a sixth impurity region of the second conductivity type on the surface of the second well region, the fourth wiring layer being on the surface of second well region between the third and sixth impurity regions, the third and sixth impurity regions being electrically connected to a second power line.

17. The semiconductor integrated circuit according to claim 16, wherein the first conductivity type is p type, and the second conductivity type is n type.

18. A semiconductor integrated circuit, comprising:

a first well region of a first conductivity type;

a second well region of a second conductivity type and adjacent to the first well region in a first direction;

a first doped region in the first well region having a conductivity type that is opposite the first conductivity type;

a second doped region in the first well region spaced from the first doped region in a second direction perpendicular to the first direction and having the conductivity type that is opposite the first conductivity type;

a third doped region in the second well region having a conductivity type that is opposite the second conductivity type;

a fourth doped region in the second well region spaced from the third doped region in the second direction and having the conductivity that is opposite the second conductivity type;

a common gate electrode layer extending in the first direction between the first and second well regions, disposed on a surface of the first well region between the first and second doped regions in the second direction, and disposed on a surface of the second well region between the third and fourth doped regions in the second direction, a gate insulating film being between the common gate electrode layer and the surfaces of the first and second well regions;

a first power line electrically connected to the first doped region;

a second power line electrically connected to the third and fourth doped regions; and

a resistive element electrically connected between the second power line and the common gate electrode layer, the resistive element comprising;

a first via contacting the third doped region and connected to the second power line,

a second via contacting on the third doped region and spaced from the first via,

a third via contacting the common gate electrode layer, and

a connecting wiring portion on the second via and the third via.

19. The semiconductor integrated circuit according to claim 18, wherein the connection wiring portion, the first power line, and the second power line are in a same wiring level at a same distance from the surfaces of the first and second well regions.

20. The semiconductor integrated circuit according to claim 18, wherein the first and second conductivity types are opposite conductivity types.