PWM Capacitor Control
First Claim
1. A variable capacitance device comprising:
- a capacitor;
a first transistor comprising a first-transistor source terminal, a first-transistor drain terminal, and a first-transistor gate terminal, the first-transistor drain terminal electrically connected to a first terminal of the capacitor;
a second transistor comprising a second-transistor source terminal, a second-transistor drain terminal, and a second-transistor a gate terminal, the second-transistor drain terminal electrically connected to a second terminal of the capacitor, and the second-transistor source terminal electrically connected to the second-transistor source terminal; and
control circuitry coupled to the first-transistor gate terminal and the second-transistor gate terminal,wherein the control circuitry is configured to adjust an effective capacitance of the capacitor by performing operations comprising;
detecting a first zero-crossing of an input current at a first time;
after a first delay period from the first time, switching off the first transistor, wherein a length of the first delay period is controlled by an input value;
detecting a second zero-crossing of the input current at a second time, after the first time;
measuring an elapsed time between switching off the first transistor and detecting the second zero-crossing;
setting a counter based on the elapsed time; and
after a second delay period based on the counter, switching on the first transistor.
1 Assignment
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Accused Products
Abstract
Methods, systems, and devices for controlling a variable capacitor. One aspect features a variable capacitance device that includes a capacitor, a first transistor, a second transistor, and control circuitry. The control circuitry is configured to adjust an effective capacitance of the capacitor by performing operations including detecting a zero-crossing of an input current at a first time. Switching off the first transistor. Estimating a first delay period for switching the first transistor on when a voltage across the capacitor is zero. Switching on the first transistor after the first delay period from the first time. Detecting a zero-crossing of the input current at a second time. Switching off the second transistor. Estimating a second delay period for switching the second transistor on when a voltage across the capacitor is zero. Switching on the second transistor after the second delay period from the second time.
25 Citations
20 Claims
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1. A variable capacitance device comprising:
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a capacitor; a first transistor comprising a first-transistor source terminal, a first-transistor drain terminal, and a first-transistor gate terminal, the first-transistor drain terminal electrically connected to a first terminal of the capacitor; a second transistor comprising a second-transistor source terminal, a second-transistor drain terminal, and a second-transistor a gate terminal, the second-transistor drain terminal electrically connected to a second terminal of the capacitor, and the second-transistor source terminal electrically connected to the second-transistor source terminal; and control circuitry coupled to the first-transistor gate terminal and the second-transistor gate terminal, wherein the control circuitry is configured to adjust an effective capacitance of the capacitor by performing operations comprising; detecting a first zero-crossing of an input current at a first time; after a first delay period from the first time, switching off the first transistor, wherein a length of the first delay period is controlled by an input value; detecting a second zero-crossing of the input current at a second time, after the first time; measuring an elapsed time between switching off the first transistor and detecting the second zero-crossing; setting a counter based on the elapsed time; and after a second delay period based on the counter, switching on the first transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A variable capacitance device comprising:
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a capacitor; a first transistor comprising a first-transistor source terminal, a first-transistor drain terminal, and a first-transistor gate terminal, the first-transistor drain terminal electrically connected to a first terminal of the capacitor; a second transistor comprising a second-transistor source terminal, a second-transistor drain terminal, and a second-transistor a gate terminal, the second-transistor drain terminal electrically connected to a second terminal of the capacitor, and the second-transistor source terminal electrically connected to the second-transistor source terminal; and control circuitry coupled to the first-transistor gate terminal and the second-transistor gate terminal, wherein the control circuitry is configured to adjust an effective capacitance of the capacitor by performing operations comprising; detecting a zero-crossing of an input current at a first time; switching off the first transistor; estimating, based on an input value, a first delay period for switching the first transistor on when a voltage across the capacitor is zero; after the first delay period from the first time, switching on the first transistor; detecting a zero-crossing of the input current at a second time; switching off the second transistor; estimating, based on the input value, a second delay period for switching the second transistor on when a voltage across the capacitor is zero; and after the second delay period from the second time, switching on the second transistor. - View Dependent Claims (11, 12, 13, 14)
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15. A variable capacitance device comprising:
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a capacitor; a first transistor comprising a first-transistor source terminal, a first-transistor drain terminal, and a first-transistor gate terminal, the first-transistor drain terminal electrically connected to a first terminal of the capacitor; a second transistor comprising a second-transistor source terminal, a second-transistor drain terminal, and a second-transistor a gate terminal, the second-transistor drain terminal electrically connected to a second terminal of the capacitor, and the second-transistor source terminal electrically connected to the second-transistor source terminal; and control circuitry coupled to the first-transistor gate terminal and the second-transistor gate terminal, wherein the control circuitry is configured to adjust an effective capacitance of the capacitor by performing operations comprising; switching off the first transistor at a first time; switching on the first transistor after detecting a current through a first diode associated with the first transistor; switching off the second transistor at a second time; and switching on the second transistor after detecting a current through a second diode associated with the second transistor. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification