SYSTEMS AND METHODS FOR CONTROLLING MULTI-LEVEL DIODE-CLAMPED INVERTERS USING SPACE VECTOR PULSE WIDTH MODULATION (SVPWM)
First Claim
1. A control system for a multi-level inverter, comprising:
- a digital logic circuit comprising;
a plurality of digital logic comparators including a first comparator and a second comparator;
a plurality of inverters coupled to respective outputs of a respective plurality of comparators, the plurality of inverters including a first inverter; and
a plurality of AND gates including an AND gate, the AND gate having a first input and a second input, the first input coupled to the output of the first inverter and the second input coupled to the output of the second comparator;
a digital up/down counter coupled to first inputs of the plurality of comparators, the up/down counter counting from 0 to Ts/2 and then from Ts/2 to 0, where Ts is a sampling period; and
a processor and memory configured to;
identify a sector location based on an actual angle of a reference voltage vector;
convert the actual angle into a converted angle located in a first sector;
identify a reference region location based on the magnitude of the reference voltage vector and the converted angle in the first sector;
select a switching sequence and turn-on time values based on the corresponding actual region location and actual sector;
transmit turn-on time values to second inputs of the plurality of comparators; and
provide the output of the first comparator, the outputs of the plurality of AND gates, and the output of a last inverter of the plurality of inverters as switching signals, which are transmitted to gate drivers for driving power transistors of the multi-level inverter.
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Abstract
Control systems for a multi-level diode-clamped inverter and corresponding methods include a processor and a digital logic circuit forming a hybrid controller. The processor identifies sector and region locations based on a sampled reference voltage vector V* and angle θe*. The processor then selects predefined switching sequences and pre-calculated turn-on time values based on the identified sector and region locations. The digital logic circuit generates PWM switching signals for driving power transistors of a multi-level diode-clamped inverter based on the turn-on time values and the selected switching sequences. The control system takes care of the existing capacitor voltage balancing issues of multi-level diode-clamped inverters while supplying both active and reactive power to an IT load. Using the control system, one can generate a symmetrical PWM signal that fully covers the linear under-modulation region.
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Citations
18 Claims
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1. A control system for a multi-level inverter, comprising:
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a digital logic circuit comprising; a plurality of digital logic comparators including a first comparator and a second comparator; a plurality of inverters coupled to respective outputs of a respective plurality of comparators, the plurality of inverters including a first inverter; and a plurality of AND gates including an AND gate, the AND gate having a first input and a second input, the first input coupled to the output of the first inverter and the second input coupled to the output of the second comparator; a digital up/down counter coupled to first inputs of the plurality of comparators, the up/down counter counting from 0 to Ts/2 and then from Ts/2 to 0, where Ts is a sampling period; and a processor and memory configured to; identify a sector location based on an actual angle of a reference voltage vector; convert the actual angle into a converted angle located in a first sector; identify a reference region location based on the magnitude of the reference voltage vector and the converted angle in the first sector; select a switching sequence and turn-on time values based on the corresponding actual region location and actual sector; transmit turn-on time values to second inputs of the plurality of comparators; and provide the output of the first comparator, the outputs of the plurality of AND gates, and the output of a last inverter of the plurality of inverters as switching signals, which are transmitted to gate drivers for driving power transistors of the multi-level inverter. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method of controlling a multi-level inverter, comprising:
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identifying a sector location based on an actual angle of a reference voltage vector; converting the actual angle into a converted angle located in a first sector; identifying a region location based on the magnitude of the reference voltage vector and the converted angle in the first sector; selecting a switching sequence and a plurality of turn-on time values based on the corresponding region location in actual sector of reference voltage vector; transmitting the turn-on time values to second inputs of the plurality of comparators to generate switching signals, which are transmitted to gate drivers for driving power transistors of the multi-level inverter; comparing each of the plurality of turn-on signals to a digital up/down counter signal to obtain a plurality of comparison signals including a first comparison signal and a second comparison signal; inverting the plurality of comparison signals to obtain a plurality of inverted signals including a first inverted signal; and performing a logical AND operation on the first inverted signal and the second comparison signal to obtain a switching signal, which is transmitted to a gate driver for driving a power transistor of the multi-level inverter. - View Dependent Claims (13, 14, 15, 16, 17)
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18. An energy storage system comprising:
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an energy storage device; a DC-DC converter coupled to the energy storage device; a multi-level inverter coupled to the DC-DC converter; and a controller for the multi-level inverter, the controller comprising; a digital logic circuit comprising; a plurality of comparators including a first comparator and a second comparator; a plurality of inverters coupled to respective outputs of a respective plurality of comparators, the plurality of inverters including a first inverter; and a plurality of AND gates including a first AND gate, the first AND gate having a first input and a second input, the first input coupled to the output of the first inverter and the second input coupled to the output of the second comparator; a counter coupled to first inputs of the plurality of comparators; and a processor and memory configured to; identify a sector location based on an actual angle of a reference voltage vector; convert the actual angle into a converted angle located in a first sector; identify a region location based on the magnitude of the reference voltage vector and the converted angle in the first sector; select a switching sequence and turn-on signal values based on the corresponding region and actual reference voltage vector location; transmit turn-on signal values to second inputs of the plurality of comparators; and provide the output of the first comparator, the outputs of the plurality of AND gates, and the output of a last inverter of the plurality of inverters as switching signals, which are transmitted to gate drivers for driving power transistors of the multi-level inverter.
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Specification