APPARATUSES AND METHODS FOR DATA MOVEMENT
First Claim
1. An apparatus, comprising:
- a memory device, comprising;
a plurality of subarrays of memory cells;
sensing circuitry coupled to the plurality of subarrays, the sensing circuitry including a sense amplifier and a compute component; and
a plurality of subarray controllers, wherein each subarray controller of the plurality of subarray controllers is coupled to a respective subarray of the plurality of subarrays and is configured to direct performance of an operation with respect to data stored in the respective subarray of the plurality of subarrays; and
wherein the memory device is configured to move a data value corresponding to a result of an operation with respect to data stored in a first subarray of the plurality of subarrays to a memory cell in a second subarray of the plurality of subarrays.
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Accused Products
Abstract
The present disclosure includes apparatuses and methods for data movement. An example apparatus includes a memory device that includes a plurality of subarrays of memory cells and sensing circuitry coupled to the plurality of subarrays. The sensing circuitry includes a sense amplifier and a compute component. The memory device also includes a plurality of subarray controllers. Each subarray controller of the plurality of subarray controllers is coupled to a respective subarray of the plurality of subarrays and is configured to direct performance of an operation with respect to data stored in the respective subarray of the plurality of subarrays. The memory device is configured to move a data value corresponding to a result of an operation with respect to data stored in a first subarray of the plurality of subarrays to a memory cell in a second subarray of the plurality of subarrays.
73 Citations
33 Claims
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1. An apparatus, comprising:
a memory device, comprising; a plurality of subarrays of memory cells; sensing circuitry coupled to the plurality of subarrays, the sensing circuitry including a sense amplifier and a compute component; and a plurality of subarray controllers, wherein each subarray controller of the plurality of subarray controllers is coupled to a respective subarray of the plurality of subarrays and is configured to direct performance of an operation with respect to data stored in the respective subarray of the plurality of subarrays; and wherein the memory device is configured to move a data value corresponding to a result of an operation with respect to data stored in a first subarray of the plurality of subarrays to a memory cell in a second subarray of the plurality of subarrays. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An apparatus, comprising:
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a controller coupled to a bank of a memory device to execute a command for movement of data in the bank, wherein the bank in the memory device comprises; a plurality of subarrays of memory cells; a plurality of subarray controllers, wherein each subarray controller of the plurality of subarray controllers is coupled to a respective subarray of the plurality of subarrays and is configured to direct performance of an operation with respect to data stored in the respective subarray of the plurality of subarrays; and sensing circuitry on pitch with the plurality of subarrays and coupled to the plurality of subarrays via a plurality of sense lines, the sensing circuitry including a sense amplifier and a compute component coupled to a respective sense line of the plurality of sense lines; and wherein the controller is configured to provide a respective set of instructions to each of the plurality of subarray controllers. - View Dependent Claims (12, 13, 14, 15, 16)
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17. An apparatus, comprising:
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a controller coupled to a bank of a memory device to execute a command for movement of data from a start location to an end location in the bank, wherein the bank in the memory device comprises; a plurality of subarrays of memory cells; a plurality of subarray controllers, wherein each subarray controller of the plurality of subarray controllers is coupled to a respective subarray of the plurality of subarrays and is configured to direct performance of an operation with respect to data stored in the respective subarray of the plurality of subarrays; and sensing circuitry coupled to the plurality of subarrays via a plurality of sense lines, the sensing circuitry including a sense amplifier and a compute component coupled to a respective sense line of the plurality of sense lines; and wherein the plurality of subarray controllers is configured to couple to the controller to receive a respective set of instructions by each of the plurality of subarray controllers to direct performance of the operation with respect to data stored in each of the plurality of subarrays. - View Dependent Claims (18, 19, 20, 21, 22)
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23. A method for operating a memory device, comprising:
executing non-transitory instructions by a processing resource for; performing a first operation on data values stored by memory cells in a particular row in a first subarray by execution of a first set of instructions, wherein the first set of instructions is executed by a first subarray controller for the first sub array; moving the data values, upon which the first operation has been performed, to a selected row of memory cells in a second subarray using a first sensing component stripe for the first subarray; and performing a second operation on the data values moved to the selected row of the second subarray by execution of a second set of instructions, wherein the second set of instructions is executed by a second subarray controller for the second subarray. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31, 32, 33)
Specification