TRUST ARCHITECTURE AND RELATED METHODS

• US 20170235961A1
• Filed: 10/21/2015
• Published: 08/17/2017
• Est. Priority Date: 10/21/2014
• Status: Active Grant

• Current Assignee: The Trustees of Princeton University (Princeton University)
• Original Assignee: Princeton University
• Inventors: AUGUST, David I., GHOSH, Soumyadeep, FIX, Jordan
• Granted Patent: US 10,599,853 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/3466 Performance evaluation by tracing or monitoring
• CPC Class Codes: G06F 21/577 Assessing vulnerabilities and evaluating computer system security
• CPC Class Codes: G06F 21/64 Protecting data integrity, e.g. using checksums, certificates or signatures
• CPC Class Codes: G06F 21/75 by inhibiting the analysis of circuitry or operation
• CPC Class Codes: G06F 2221/034 Test or assess a computer or a system
• CPC Class Codes: H04L 9/3242 involving keyed hash functions, e.g. message authentication codes [MACs], CBC-MAC or HMAC

Abstract

A pluggable trust architecture addresses the problem of establishing trust in hardware. The architecture has low impact on system performance and comprises a simple, user-supplied, and pluggable hardware element. The hardware element physically separates the untrusted components of a system from peripheral components that communicate with the external world. The invention only allows results of correct execution of software to be communicated externally.

Claims

1. In a computer system, a method for establishing trust in hardware components comprising the steps of:

executing by a processor one or more instructions, producing untrusted trace information;

sending by the processor the entrusted trace information to a hardware element;

receiving by the hardware element the untrusted trace information;

examining by the hardware element at least the aspects of the untrusted trace information intended to generate computer system output to a device;

producing by the hardware element computer system output to a device only when the aspects examined are correct.

2. The method of claim 1, wherein the examining step further comprises the step of:

checking one or more of the following;

correctness of execution of all instructions;

correctness of execution of instructions influencing communication external to the computer system;

integrity of memory instructions;

integrity of code being executed; and

correctness of signatures of installed software.

3. The method of claim 1, wherein the receiving step further comprises the step of buffering by the hardware element the untrusted trace information in an incoming buffer.

4. The method of claim 1, wherein the aspects of the untrusted trace information comprise one or more selected from the group:

an instruction, an operand, a result, and a MAC (Message Authentication Code) value.

5. The method of claim 4, wherein the one or more MAC values are hash values.

6. The method of claim 1, wherein the examining step further comprises the steps of:

re-executing by the hardware element the one or more instructions, producing trusted trace information; and

comparing by the hardware element the aspects of the untrusted trace information to the trusted trace information.

7. The method according to claim 1, wherein the examining step further comprises the steps of:

writing by the hardware element results from the untrusted trace information to one or more pipeline registers and a shadow register file;

fetching by the hardware element the one or more instructions from an incoming buffer;

sending one or more operands to the one or more pipeline registers;

executing the one or more instructions using the one or more operands in the one or more pipeline registers;

comparing results of the executing step against results of the untrusted trace information; and

determining computer system output when both results are equal.

8. The method according to claim 7, wherein the writing step further comprises the steps of:

verifying by the hardware element that only a value corresponding to an instruction that appears later in a commit order of the processor is written to the shadow register file when two or more instructions try to write to the same shadow register file;

simultaneously verifying execution of the two or more instructions in parallel; and

9. The method according to claim 8 further comprising the step of breaking dependencies between the two or more instructions using the untrusted trace information.

10. The method according to claim 7, wherein the fetching step further comprises the step of decoding the one or more instructions.

11. The method of claim 1, wherein the examining step further comprises the step of:

allowing by the hardware element computer system output to a device only when the aspects examined are correct.

12. The method according to claim 1, wherein one or more instructions executed by the processor are memory instructions comprising one or more of the following:

a store operation to write values into the memory and a load operation to load values from the memory.

13. The method according to claim 12, wherein the hardware element uses one or more message authentication codes (MAC) for cryptographic verification of data loaded from or stored to the memory.

14. The method according to claim 12, where the cryptographic verification of a store operation comprises the steps of:

generating by the hardware element a message authentication code (MAC) value corresponding to each store, each MAC value based on a stored value, a memory, store address, and a secret key;

storing each MAC value in a buffer of the hardware element;

sending by the hardware element one or more MAC values to the processor;

storing by the processor the one or more MAC values to a shadow memory.

15. The method according to claim 12, where the cryptographic verification of a load operation comprises the steps of:

sending by the processor a value loaded from the memory and a corresponding loaded message authentication code (MAC) value to the hardware element as part of the untrusted trace information;

generating by the hardware element a MAC value corresponding to each load, each MAC value based on a loaded value, a memory load address, and a secret key;

determining by the hardware element if the loaded MAC value and the generated MAC value are equal.

16. The method according to claim 15, wherein the determining step further comprises the steps of:

comparing the generated MAC value with a MAC value in a buffer if the buffer contains an entry for the memory load address;

or

comparing the generated MAC with the loaded MAC value sent as part of the untrusted trace information.

17. The method according to claim 1 further comprising the steps of:

populating by the processor a cache in the hardware element with one or more instructions to be verified or that have been verified by the hardware element.

18. A pluggable trust architecture comprising:

a processor,

a hardware element for receiving execution information from the processor to detect at least one form of incorrect execution by the processor without relying on any execution information to be correct; and

a barrier circuit for preventing any computer system output to a device resulting from incorrect execution.

19. The pluggable trust architecture according to claim 18, wherein the hardware element detects incorrect execution of instructions affecting output via peripheral components, and the barrier circuit includes an electrical barrier capable of preventing output via peripheral components.

20. The pluggable trust architecture according to claim 18, wherein a portion of one or more of the hardware element and the barrier circuit are removable and output is prevented when the portion is removed from the hardware element.

21. The pluggable trust architecture according to claim 18, wherein the hardware element further comprises:

a buffer for storing entrusted trace information sent by the processor;

a verification engine for checking correctness of instructions; and

a MAC (Message Authentication Code) generator for checking integrity of the memory and a program code.

22. The pluggable trust architecture according to claim 18, wherein the hardware element further comprises:

a shadow register file to verify one or more operands used by the processor;

an outgoing buffer enabling memory integrity checks; and

an incoming buffer for containing the results of instructions causing output to devices that are waiting to be verified.