MEMORY DEVICE ULTRA-DEEP POWER-DOWN MODE EXIT CONTROL

• US 20170236561A1
• Filed: 01/18/2017
• Published: 08/17/2017
• Est. Priority Date: 02/11/2016
• Status: Active Grant

• Current Assignee: Adesto Technologies Corporation (Renesas Electronics Corporation)
• Original Assignee: Adesto Technologies Corporation (Renesas Electronics Corporation)
• Inventors: Pedersen, Bard M., Gonzales, Nathan, Dinh, John, Lewis, Derric, Intrater, Gideon
• Granted Patent: US 9,922,684 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 5/148 Details of power up or power down circuits, standby circuits or recovery circuits

Abstract

A memory device operable in an ultra-deep power-down mode can include: a command user interface; a voltage regulator having an output that provides a supply voltage for a plurality of components of the memory device, where the plurality of components comprises the command user interface; a wake-up circuit that remains powered on even when the memory device is in the ultra-deep power-down mode; the memory device being operable to enter the ultra-deep power-down mode in response to receiving a first predetermined command that causes the output of the voltage regulator to be disabled to completely power down the plurality of components during the ultra-deep power-down mode; and the memory device being operable to exit the ultra-deep power-down mode in response to receiving one of a hardware reset command sequence, a reset pin assertion, a power supply cycling, and a second predetermined command.

Claims

1. A memory device operable in an ultra-deep power-down mode, the memory device comprising:

a) a command user interface;

b) a voltage regulator having an output that provides a supply voltage for a plurality of components of the memory device, wherein the plurality of components comprises the command user interface;

c) a wake-up circuit that remains powered on even when the memory device is in the ultra-deep power-down mode;

d) the memory device being operable to enter the ultra-deep power-down mode in response to receiving a first predetermined command that causes the output of the voltage regulator to be disabled to completely power down the plurality of components during the ultra-deep power-down mode; and

e) the memory device being operable to exit the ultra-deep power-down mode in response to receiving one of a hardware reset command sequence, a reset pin assertion, a power supply cycling, and a second predetermined command, thereby causing the output of the voltage regulator to be enabled to provide power to the plurality of components.

2. The memory device of claim 1, wherein the hardware reset command sequence comprises a chip select signal being activated, a clock signal remaining stable, a serial input signal being driven low simultaneously with the chip select signal being activated, and the chip select signal being deactivated.

3. The memory device of claim 2, wherein the hardware reset command sequence further comprises alternating the state of the serial input signal in three subsequent repetitions.

4. The memory device of claim 1, wherein the reset pin assertion comprises activating the reset pin for at least a predetermined time.

5. The memory device of claim 1, wherein the power supply cycling comprises disabling a main power supply to the memory device, and then enabling the main power supply.

6. The memory device of claim 1, wherein the second predetermined command comprises an opcode provided on a serial input signal.

7. The memory device of claim 6, wherein the opcode is received over a plurality of cycles of a clock signal.

8. The memory device of claim 6, wherein the opcode is received over a single cycle of a clock signal when the memory device is in an octal configuration.

9. The memory device of claim 1, being configured in a single SPI mode upon exiting the ultra-deep power-down mode.

10. The memory device of claim 1, wherein the second predetermined command excludes a status register read command.

19. An apparatus comprising the memory device of claim 1, the apparatus further comprising:

a) a serial interface coupled between a host device and the memory device; and

b) the host device to being configured to provide the first and second predetermined commands, the hardware reset command sequence, and the reset pin assertion on the serial interface.

11. A method of controlling a memory device operable in an ultra-deep power-down mode, the method comprising:

a) providing, by an output of a voltage regulator, a supply voltage for a plurality of components of the memory device, wherein the plurality of components comprises a command user interface, and wherein the memory device comprises a wake-up circuit that remains powered on even when the memory device is in the ultra-deep power-down mode;

b) entering the memory device into the ultra-deep power-down mode in response to receiving a first predetermined command that causes the output of the voltage regulator to be disabled to completely power down the plurality of components during the ultra-deep power-down mode; and

c) exiting the memory device from the ultra-deep power-down mode in response to receiving one of a hardware reset command sequence, a reset pin assertion, a power supply cycling, and a second predetermined command, thereby causing the output of the voltage regulator to be enabled to provide power to the plurality of components.

12. The method of claim 11, wherein the hardware reset command sequence comprises:

a) activating a chip select signal being activated;

b) maintaining a clock signal as stable;

c) driving a serial input signal low simultaneously with the chip select signal being activated; and

d) deactivating the chip select signal.

13. The method of claim 12, wherein the hardware reset command sequence further comprises alternating the state of the serial input signal in three subsequent repetitions.

14. The method of claim 11, wherein the reset pin assertion comprises activating the reset pin for at least a predetermined time.

15. The method of claim 11, wherein the power supply cycling comprises disabling a main power supply to the memory device, and then enabling the main power supply.

16. The method of claim 11, wherein the second predetermined command comprises an opcode provided on a serial input signal.

17. The method of claim 16, wherein the opcode is received over a plurality of cycles of a clock signal.

18. The method of claim 11, wherein the exiting the ultra-deep power-down mode comprises placing the memory device in a single SPI mode configuration.

20. An apparatus, comprising:

a) means for providing a supply voltage for a plurality of components of a memory device that is operable in an ultra-deep power-down mode, wherein the plurality of components comprises a command user interface, and wherein the memory device comprises circuitry that remains powered on even when the memory device is in the ultra-deep power-down mode;

b) means for placing the memory device into the ultra-deep power-down mode in response to receiving a first predetermined command that completely power downs the plurality of components during the ultra-deep power-down mode; and

c) means for exiting the ultra-deep power-down mode in response to receiving one of a hardware reset command sequence, a reset pin assertion, a power supply cycling, and a second predetermined command, thereby providing power to the plurality of components.