SEMICONDUCTOR DEVICE INCLUDING AN ANTENNA

• US 20170236776A1
• Filed: 02/17/2016
• Published: 08/17/2017
• Est. Priority Date: 02/17/2016
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Muehlbauer, Franz-Xaver, Huynh, Ngoc-Hoa, Huber, Veronika, Waechter, Claus, Maier, Dominic, Baheti, Ashutosh, Meyer-Berg, Georg, Kilger, Thomas, Trotta, Saverio, Wojnowski, Maciej
• Granted Patent: US 11,195,787 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2223/6683 for monolithic microwave integrated circuit [MMIC]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3672 Foil-like cooling fins or heat sinks being part of lead-frames H01L23/49568
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 2924/18162 of a chip with build-up interconnect
• CPC Class Codes: H01Q 1/2283 mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
• CPC Class Codes: H01Q 21/061 Two dimensional planar arrays
• CPC Class Codes: H01Q 21/065 Patch antenna array
• CPC Class Codes: H01Q 9/0407 Substantially flat resonant element parallel to ground plane, e.g. patch antenna dipole H01Q9/285; monopole H01Q9/40
• CPC Class Codes: H01Q 9/265 Open ring dipoles; Circular dipoles
• CPC Class Codes: H01Q 9/285 Planar dipole H01Q9/065 takes precedence; patch antenna H01Q9/0407

Abstract

A semiconductor device includes a semiconductor chip and a redistribution layer on a first side of the semiconductor chip. The redistribution layer is electrically coupled to the semiconductor chip. The semiconductor device includes a dielectric layer and an antenna on the dielectric layer. The dielectric layer is between the antenna and the semiconductor chip.

Claims

1. A semiconductor device comprising:

a semiconductor chip;

a redistribution layer on a first side of the semiconductor chip, the redistribution layer electrically coupled to the semiconductor chip;

a dielectric layer; and

an antenna on the dielectric layer,

wherein the dielectric layer is between the antenna and the semiconductor chip.

2. The semiconductor device of claim 1, further comprising:

an encapsulant material laterally surrounding the semiconductor chip.

3. The semiconductor device of claim 2, further comprising:

a plurality of solder balls electrically coupled to the redistribution layer.

4. The semiconductor device of claim 2, further comprising:

a conductive layer between the dielectric layer and the semiconductor chip.

5. The semiconductor device of claim 4, wherein the conductive layer is electrically coupled to the redistribution layer.

6. The semiconductor device of claim 2, wherein the antenna is electrically coupled to the semiconductor chip.

7. The semiconductor device of claim 2, wherein the antenna is electromagnetically coupled to the semiconductor chip.

8. The semiconductor device of claim 2, wherein the antenna comprises a dipole antenna, a folded dipole antenna, a ring antenna, a rectangular loop antenna, a patch antenna, or a coplanar patch antenna.

9. The semiconductor device of claim 1, further comprising:

an encapsulant material laterally surrounding the semiconductor chip;

wherein the redistribution layer is on the first side of the semiconductor chip and the encapsulant material, and

wherein the dielectric layer is on a second side of the semiconductor chip opposite to the first side.

10. The semiconductor device of claim 9, wherein the semiconductor chip is electrically coupled to the antenna through the redistribution layer, a first via through the encapsulant material, and a second via through the dielectric layer.

11. The semiconductor device of claim 1, further comprising:

a conductive layer between the dielectric layer and the semiconductor chip.

12. The semiconductor device of claim 11, wherein the semiconductor chip is electromagnetically coupled to the antenna through a slot in the conductive layer.

13. The semiconductor device of claim 11, wherein the conductive layer is electrically coupled to the redistribution layer through a via through an encapsulant material.

14. The semiconductor device of claim 11, wherein the conductive layer is directly electrically coupled to a solder ball having a diameter greater than the sum of a thickness of the semiconductor chip and the redistribution layer.

15. The semiconductor device of claim 1, wherein the dielectric layer is on a second side of the semiconductor chip opposite to the first side, the semiconductor device further comprising:

a conductive layer between the dielectric layer and the semiconductor chip, wherein the semiconductor chip is electrically coupled to the antenna through the redistribution layer and a via connection through the dielectric layer.

16. The semiconductor device of claim 1, further comprising:

an encapsulant material laterally surrounding the semiconductor chip;

wherein the redistribution layer is on the first side of the semiconductor chip and the encapsulant material, and

wherein the redistribution layer is between the dielectric layer and the semiconductor chip.

17. The semiconductor device of claim 16, wherein the redistribution layer comprises a conductive layer.

18. The semiconductor device of claim 17, wherein the semiconductor chip is electromagnetically coupled to the antenna through a slot in the conductive layer.

19. The semiconductor device of claim 16, further comprising:

a heat sink on a second side of the semiconductor chip opposite to the first side; and

a solder ball coupled to the heat sink.

20. The semiconductor device of claim 1, wherein the antenna comprises a dipole antenna, a folded dipole antenna, a ring antenna, a rectangular loop antenna, a patch antenna, or a coplanar patch antenna.

21. The semiconductor device of claim 1, wherein the semiconductor chip is proximity coupled to the antenna.

22. A method for fabricating a semiconductor device, the method comprising:

fabricating an embedded wafer level ball grid array package comprising a radio frequency semiconductor chip laterally surrounded by an encapsulant material, and a redistribution layer on the semiconductor chip and the encapsulant material;

fabricating a carrier comprising a dielectric material, an antenna on a first side of the dielectric material, and a conductive layer on a second side of the dielectric material opposite to the first side; and

attaching the embedded wafer level ball grid array package to the carrier such that the conductive layer is between the dielectric material and the semiconductor chip.

23. The method of claim 22, wherein attaching the embedded wafer level ball grid array package to the carrier comprises attaching the embedded wafer level ball grid array package to the carrier via a die attach foil.