SEMICONDUCTOR DEVICE

• US 20170236908A1
• Filed: 01/31/2017
• Published: 08/17/2017
• Est. Priority Date: 02/16/2016
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: NAITO, Tatsuya
• Granted Patent: US 10,121,866 B2
• Time in Patent Office: Days
• CPC Class Codes: G01K 13/00 Thermometers specially adapted for specific purposes
• CPC Class Codes: G01K 7/01 using semiconducting elements having PN junctions G01K7/02, G01K7/16, G01K7/30 take precedence
• CPC Class Codes: H01L 21/221 of killers
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 27/0664 Vertical bipolar transistor in combination with diodes
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0834 Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/32 the imperfections being within the semiconductor body
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/8613 Mesa PN junction diodes

Abstract

Provided is a semiconductor device having an RC-IGBT structure, the semiconductor device comprising an FWD (Free Wheel Diode) region and an IGBT (Insulated Gate Bipolar Transistor) region. Provided is a semiconductor device comprising:

a semiconductor substrate; a transistor section formed on the semiconductor substrate; a diode section formed on the semiconductor substrate and including a lifetime killer at a front surface side of the semiconductor substrate;
a gate runner provided between the transistor section and the diode section and electrically connected to a gate of the transistor section.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a transistor section formed on the semiconductor substrate;

a diode section formed on the semiconductor substrate and including a lifetime killer at a front surface side of the semiconductor substrate; and

a gate runner provided between the transistor section and the diode section and electrically connected to a gate of the transistor section.

2. The semiconductor device according to claim 1, wherein the semiconductor substrate includes a lifetime killer in at least some regions at the front surface side of the semiconductor substrate and below the gate runner.

3. The semiconductor device according to claim 1, wherein the semiconductor substrate includes a lifetime killer in an entire region at the front surface side of the semiconductor substrate and below the gate runner.

4. The semiconductor device according to claim 1, wherein the semiconductor substrate includes a lifetime killer in at least a portion at the front surface side of the semiconductor substrate and closer to the transistor section than to the gate runner.

5. The semiconductor device according to claim 1, wherein a collector region of the transistor section is formed in at least a portion below the gate runner.

6. The semiconductor device according to claim 1, wherein a collector region of the transistor section is formed in an entire region below the gate runner.

7. The semiconductor device according to claim 1, wherein a collector region of the transistor section is formed at least a portion closer to the diode section than to the gate runner.

8. The semiconductor device according to claim 1, wherein a cathode region of the diode section is not formed below the gate runner.

9. The semiconductor device according to claim 1, further comprising a well region having a conductivity type different from that of the semiconductor substrate and formed below the gate runner.

10. The semiconductor device according to claim 1, wherein

the transistor section includes a gate trench section formed on the front surface of the semiconductor substrate, and

at least a portion of the gate trench section is formed below the gate runner.

11. The semiconductor device according to claim 1, wherein the diode section is arranged at an end portion of an active region of the semiconductor device.

12. The semiconductor device according to claim 1, wherein the diode section is arranged at a corner portion of an active region of the semiconductor device.

13. The semiconductor device according to claim 1, wherein the diode section surrounds the transistor section in a planar view.

14. The semiconductor device according to claim 1, wherein the transistor section surrounds the diode section in a planar view.

15. The semiconductor device according to claim 1 further comprising:

a temperature sensor provided adjacent to the transistor section to detect signals in response to a temperature of the transistor section; and

a temperature sensor terminal electrically connected to the temperature sensor through a wiring for sensors, to which the signals detected by the temperature sensor are input.

16. The semiconductor device according to claim 15, wherein the diode section includes an isolation region to allow at least one of the gate runner and the wiring for sensors to traverse the diode section.

17. The semiconductor device according to claim 15, wherein the temperature sensor is arranged above a well region.

18. The semiconductor device according to claim 15, wherein the temperature sensor is surrounded by the transistor section.

19. The semiconductor device according to claim 15, wherein the diode section includes:

a first diode region formed at one end of an active region of the semiconductor device; and

a second diode region formed at the other end of the active region opposing to the one end.

20. The semiconductor device according to claim 19, wherein the temperature sensor is provided between the first diode region and the second diode region.

21. The semiconductor device according to claim 1 further comprising:

an emitter region of a first conductivity type formed on the front surface of the semiconductor substrate;

a base region of a second conductivity type which is different from the first conductivity type formed on the front surface of the semiconductor substrate;

an accumulating layer of the first conductivity type formed at the front surface side of the semiconductor substrate and having a higher concentration than an impurity concentration of the semiconductor substrate; and

an interlayer insulating film formed on the front surface of the semiconductor substrate;

wherein the interlayer insulating film includes a contact hole corresponding to at least some regions of the emitter region and the base region and formed to penetrate the interlayer insulating film, and

the accumulating layer is formed inside a region in which the contact hole is formed in an extending direction of a trench section included in the transistor section.

22. The semiconductor device according to claim 21, wherein the accumulating layer is formed inside a region in which the contact hole is formed in an extending direction of a trench section included in the diode section.

23. The semiconductor device according to claim 21, wherein the accumulating layer is formed in a region in which the transistor section, the diode section and the gate runner are formed.

24. The semiconductor device according to claim 21, wherein at least a portion of the accumulating layer is formed within a well region.

25. The semiconductor device according to claim 21, wherein the contact hole at the diode section side is formed to be apart from a well region in a planar view.

26. The semiconductor device according to claim 1, wherein at least a portion of an end portion of a trench section of the transistor section is formed within a well region.