Methods of Manufacturing a Power MOSFET

• US 20170236910A1
• Filed: 05/02/2017
• Published: 08/17/2017
• Est. Priority Date: 07/14/2014
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Siemieniec, Ralf, Blank, Oliver, Laforet, David, Hutzler, Michael, Ouvrard, Cedric, Yip, Li Juin
• Granted Patent: US 10,453,929 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method of manufacturing a power metal oxide semiconductor field effect transistor includes: forming a field electrode in a field plate trench in a main surface of a semiconductor substrate; forming a gate trench in the main surface, the gate trench extending in a first direction parallel to the main surface; and for a gate electrode in the gate trench, the gate electrode being made of a gate electrode material that comprises a metal. The field plate trench is formed to have an extension length in the first direction which is less than double of an extension length of the field plate trench in a second direction, the second direction being perpendicular to the first direction.

Claims

1. A method of manufacturing a power metal oxide semiconductor field effect transistor, the method comprising:

forming a gate electrode in a gate trench in a main surface of a semiconductor substrate, the gate trench extending parallel to the main surface, the gate electrode comprising a gate electrode material, the gate electrode material comprising a metal; and

forming a field electrode in a field plate trench in the main surface, the field plate trench having an extension length in a first direction which is less than double and more than half of an extension length of the field plate trench in a second direction perpendicular to the first direction, the first and the second directions being parallel to the main surface.

2. The method of claim 1, wherein forming the gate electrode in the gate trench comprises forming a layer stack of a first and a second metal layer, the first metal layer being adjacent to a gate dielectric.

3. The method of claim 2, wherein the first metal layer is a metal nitride.

4. The method of claim 2, wherein the second metal layer is tungsten or a silicide containing polysilicon layer.

5. The method of claim 1, wherein a width of the gate trench measured perpendicularly to the first direction is less than 500 nm.

6. The method of claim 1, further comprising:

forming a source region adjacent to the main surface

forming a drain region adjacent to a backside surface of the semiconductor substrate opposite the main surface; and

forming a body region adjacent to the gate electrode.

7. The method of claim 6, further comprising:

forming a drift zone between the body region and the drain region.

8. The method of claim 6, wherein:

forming the gate electrode comprises filling a dummy material into the gate trench; and

forming the source, drain and body regions is performed after filling the dummy material into the gate trench.

9. The method of claim 8, further comprising:

removing the dummy material from the gate trench after forming the source and the drain regions; and

filling the gate electrode material into the gate trenches after removing the dummy material from the gate trench.

10. The method of claim 1, further comprising:

forming a plurality of field plate trenches arranged along the first direction between two adjacent gate trenches.

11. The method of claim 1, further comprising:

forming a plurality of transistor cells configured to be controlled by the gate electrode.

12. The method of claim 1, wherein a width of the gate trench measured perpendicularly to the first direction is smaller than a width of the field plate trench measured perpendicularly to the first direction.

13. The method of claim 1, further comprising:

forming a gate dielectric in the gate trench that separates the gate electrode from the semiconductor substrate, the gate dielectric having a thickness of 20 to 100 nm.

14. A method of manufacturing a power metal oxide semiconductor field effect transistor, the method comprising:

forming a gate electrode in a gate trench in a main surface of a semiconductor substrate, the gate trench extending parallel to the main surface, the gate electrode comprising a gate electrode material, the gate electrode material comprising a metal; and

forming a field electrode in a field plate trench in the main surface, the field plate trench being separate from the gate trench and having an extension length parallel to the main surface which is less than a depth of the field plate trench.

15. The method of claim 14, wherein the extension length of the field plate trench is less than 0.2 times the depth of the field plate trench.

16. A method of manufacturing a power metal oxide semiconductor field effect transistor, the method comprising:

forming a field electrode in a field plate trench in a main surface of a semiconductor substrate;

forming a gate trench in the main surface, the gate trench extending in a first direction parallel to the main surface; and

forming a gate electrode in the gate trench, the gate electrode being made of a gate electrode material that comprises a metal,

wherein the field plate trench is formed to have an extension length in the first direction which is less than double of an extension length of the field plate trench in a second direction, the second direction being perpendicular to the first direction.

17. The method of claim 16, further comprising:

forming a source region adjacent to the main surface; and

forming a drain region adjacent to a backside surface of the semiconductor substrate opposite the main surface.

18. The method of claim 17, wherein the gate electrode material is formed after forming the source and the drain regions.

19. The method of claim 18, wherein:

forming the gate electrode comprises filling a dummy material into the gate trench; and

forming the source and the drain regions is performed after filling the dummy material into the gate trench.

20. The method of claim 19, further comprising:

removing the dummy material from the gate trench after forming the source and the drain regions; and

filling the gate electrode material into the gate trenches after removing the dummy material from the gate trench.