Processor Comprising Three-Dimensional Memory (3D-M) Array
First Claim
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1. A three-dimensional processor (3D-processor), comprising:
- a semiconductor substrate including transistors thereon;
at least a computing element formed on said semiconductor substrate, said computing element comprising an arithmetic logic circuit (ALC) and a three-dimensional memory (3D-M)-based look-up table (3DM-LUT), whereinsaid ALC is formed on said semiconductor substrate and configured to perform at least one arithmetic operation on data from said 3DM-LUT;
said 3DM-LUT is stored in at least a 3D-M array, said 3D-M array being stacked above said ALC;
said 3D-M array and said ALC are communicatively coupled by a plurality of contact vias.
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Abstract
The present invention discloses a processor comprising three-dimensional memory (3D-M) array (3D-processor). Instead of logic-based computation (LBC), the 3D-processor uses memory-based computation (MBC). It comprises an array of computing elements, with each computing element comprising an arithmetic logic circuit (ALC) and a 3D-M-based look-up table (3DM-LUT). The ALC performs arithmetic operations on the LUT data, while the 3DM-LUT is stored in at least one 3D-M array.
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20 Claims
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1. A three-dimensional processor (3D-processor), comprising:
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a semiconductor substrate including transistors thereon; at least a computing element formed on said semiconductor substrate, said computing element comprising an arithmetic logic circuit (ALC) and a three-dimensional memory (3D-M)-based look-up table (3DM-LUT), wherein said ALC is formed on said semiconductor substrate and configured to perform at least one arithmetic operation on data from said 3DM-LUT; said 3DM-LUT is stored in at least a 3D-M array, said 3D-M array being stacked above said ALC; said 3D-M array and said ALC are communicatively coupled by a plurality of contact vias. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification