Integrated RF Front End with Stacked Transistor Switch

• US 20170237462A1
• Filed: 05/03/2017
• Published: 08/17/2017
• Est. Priority Date: 06/23/2004
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Burgener, Mark L., Cable, James S.
• Granted Patent: US 9,966,988 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01Q 23/00 Antennas with active circuits or circuit elements integrated within them or attached to them
• CPC Class Codes: H03F 1/0205 in transistor amplifiers
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 1/56 Modifications of input or output impedances, not otherwise provided for
• CPC Class Codes: H03F 1/565 using inductive elements
• CPC Class Codes: H03F 2200/294 the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/372 Noise reduction and elimination in amplifier
• CPC Class Codes: H03F 2200/387 A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2200/61 the cascode amplifier has more than one common gate stage
• CPC Class Codes: H03F 3/189 High-frequency amplifiers, e.g. radio frequency amplifiers
• CPC Class Codes: H03F 3/19 with semiconductor devices only
• CPC Class Codes: H03F 3/21 with semiconductor devices only H03F3/245 takes precedence
• CPC Class Codes: H03F 3/2171 with field-effect devices H03F3/2173 - H03F3/2178 take precedence
• CPC Class Codes: H03F 3/68 Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602
• CPC Class Codes: H03G 11/00 Limiting amplitude; Limiting rate of change of amplitude ; Clipping in general
• CPC Class Codes: H03G 3/3042 in modulators, frequency-changers, transmitters or power amplifiers transmission power control in bidirectional transmission systems H04W52/04
• CPC Class Codes: H04B 1/0053 with common antenna for more than one band
• CPC Class Codes: H04B 1/0475 with means for limiting noise, interference or distortion H04B1/0483 takes precedence
• CPC Class Codes: H04B 1/48 : in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter H04B1/46 takes precedence
• CPC Class Codes: H04L 27/04 : Modulator circuits; Transmitter circuits

Abstract

A monolithic integrated circuit (IC), and method of manufacturing same, that includes all RF front end or transceiver elements for a portable communication device, including a power amplifier (PA), a matching, coupling and filtering network, and an antenna switch to couple the conditioned PA signal to an antenna. An output signal sensor senses at least a voltage amplitude of the signal switched by the antenna switch, and signals a PA control circuit to limit PA output power in response to excessive values of sensed output. Stacks of multiple FETs in series to operate as a switching device may be used for implementation of the RF front end, and the method and apparatus of such stacks are claimed as subcombinations. An iClass PA architecture is described that dissipatively terminates unwanted harmonics of the PA output signal. A preferred embodiment of the RF transceiver IC includes two distinct PA circuits, two distinct receive signal amplifier circuits, and a four-way antenna switch to selectably couple a single antenna connection to any one of the four circuits.

Claims

1. (canceled)

2. An integrated RF Power Amplifier (PA) circuit, comprising:

a. an input node to accept an input signal with respect to a reference voltage Vref, the input node connected to a first gate of a first MOSFET, wherein a source of MOSFET is connected to Vref;

b. one or more MOSFETs connected in series with the first MOSFET to form a transistor stack, wherein the first MOSFET comprises a bottom transistor of the transistor stack, and the one or more MOSFETs comprises a top transistor of the transistor stack, wherein the transistor stack is configured to control conduction between the reference voltage Vref and an output drive node, and wherein the output drive node is connected to a drain of the top transistor of the transistor stack; and

c. one or more predominantly capacitive elements connected directly between a corresponding gate of the one or more MOSFETs and Vref.

3. The integrated RF PA circuit of claim 2, wherein the one or more MOSFETs comprises a plurality of MOSFETs.

4. The integrated RF PA circuit of claim 2, further comprising a bias choke connecting the output driver node to a power supply.

5. The integrated RF PA circuit of claim 4, wherein the bias choke is on-chip.

6. The integrated RF PA circuit of claim 4, wherein the bias choke is off-chip.

7. The integrated RF PA of claim 2, further comprising a matching, coupling and filtering circuit connected to the output drive node, wherein the matching, coupling and filtering circuit is disposed between the output drive node and an external antenna.

8. The integrated RF PA circuit of claim 7, wherein the matching, coupling, and filtering circuit is on-chip.

9. The integrated RF PA circuit of claim 7, wherein the matching, coupling, and filtering circuit is off-chip.

10. The integrated RF PA circuit of claim 7, wherein the matching, coupling, and filtering circuits are fabricated as a combination of both on-chip and off chip elements.

11. The integrated RF PA circuit of claim 2, wherein:

(a) each gate of the one or more MOSFETs is connected to a corresponding bias resistor of one or more bias resistors;

(b) each bias resistor of the one or more bias resistors is connected to a corresponding bias voltage of one or more bias voltages, and

(c) each bias voltage of the one or more bias voltages may be individually selected to adjust a DC voltage divided across each MOSFET of the one or MOSFETS, and

The DC voltage divided across each MOSFET of the one or more MOSFETs may be controlled by the one or more bias voltages to produce desired DC voltages across MOSFETS of the one or more MOSFETs

12. The integrated RF PA of claim 11, wherein the desired DC voltages across MOSFETs of the one or more MOSFETs are identical.

13. The integrated RF PA of claim 2, wherein a gate capacitor of one or more gate capacitors connects a corresponding gate of the one or more MOSFETs to a ground reference, and wherein RF voltages across MOSFETs of the one or more MOSFETs are determined by capacitances of the corresponding gate capacitors of the one or more gate capacitors.

14. The integrated RF PA of claim 13, wherein DC and the RF voltages across MOSFETs of the one or more MOSFETs are:

(i) controlled by corresponding bias voltage of one or more bias voltages, and the corresponding gate capacitors of the one or more gate capacitors respectively

(ii) independently controlled.

15. The integrated RF PA of claim 14, wherein the DC voltages across MOSFETs of the one or more MOSFETs are approximately equal.

16. The integrated RF PA of claim 14, wherein the RF voltages across MOSFETs of the one or more MOSFETs are approximately equal.

17. The integrated RF PA of claim 14, wherein the DC voltages across MOSFETs of the one or more MOSFETs are set to desired values.

18. The integrated RF PA of claim 14, wherein the RF voltages across MOSFETs of one or more MOSFETs are set to desired values.

19. The integrated RF PA of claim 2 wherein the one ore more MOSFETs are fabricated in a silicon layer of a silicon-on-insulator (SOI) substrate.

20. The integrated RF PA of claim 19, wherein the one or more MOSFETs have corresponding sources and drains, and wherein the sources and the drains extend through an entire thickness of the silicon layer and further down to an insulating layer of the SOI substrate.

21. The integrated RF PA of claim 2, wherein the first MOSFET and the one or more MOSFETs have approximately equal voltages across their corresponding drains-sources.

22. The integrated RF PA of claim 2, wherein the first MOSFET and the one or more MOSFETs have unequal voltages across their corresponding drains-sources.

23. The integrated RF PA of claim 2, wherein DC voltages across transistors of the transistor stack are equal.

24. The integrated RF PA of claim 2, wherein DC voltages across transistors of the transistor stack are unequal

25. The integrated RF PA of claim 7, further comprising an output filter section connected in series with the matching, coupling and filtering circuit and disposed between the matching, coupling and filtering circuit and an RF switch, wherein the RF switch connects the output filter section to the external antenna when the RF switch is in an ON (conducting) state.

26. The circuit of claim 2, wherein the RF PA comprises a Class A, B, or C, AB, or F RF PA.

27. A multiple-MOSFET stack circuit for controlling conduction between a drive output node Vdrive and a reference voltage node Vref under control of an input signal applied between an input signal node and Vref, the circuit comprising:

a. a series transistor stack of J MOSFETs M_N, N being an integer between 1 and J and J being an integer 2 or greater, each MOSFET M_N having a source S_N, a gate G_N and a drain D_N,

b. an input signal node connected to the gate G₁ of a signal-input MOSFET M₁ of the MOSFET stack;

c. for 0<

N<

J, a series coupling between each drain D_N and the source S_(N+1) of a next higher MOSFET M_(N+1) of the MOSFET transistor stack;

d. for 1<

N≦

J, a gate coupling element that is predominately capacitive connected directly between each gate G_N and Vref, wherein, for 1<

N≦

J, each MOSFET M_N is biased to avoid exceeding breakdown characteristics of the FET M_N; and

where each gate G_N is provided with a suitable bias voltage, and wherein the bias voltage is decoupled to Vref;

e. a source coupling for the FET stack between S₁ and Vref; and

f. a drain coupling for the FET stack between D_J and Vdrive;

wherein both RF and DC voltages are divided across the transistor stack, and wherein each MOSFET M₂ to M_N has associated and corresponding bias voltages VB₂ to VB_N, wherein the bias voltages VB₂ to VB_N may be individually selected to adjust the DC voltage divided across each corresponding and associated MOSFET M₂ to M_N, and wherein the divided DC voltage across each MOSFET M₂ to M_N may be controlled by the bias voltages VB₂ to VB_N to be identical, or they may be controlled by the bias voltages to be any desired divided DC voltage.

28. The multiple-MOSFET stack circuit of claim 27, wherein J is an integer 3 or greater.

29. The multiple-MOSFET stack circuit of claim 27, wherein each MOSFET M₂ to M_N has associated and corresponding bias resistors RB₂ to RB_N connected to their associated and corresponding gates of G₂ to G_N, wherein the bias resistors RB₂ to RB_N are connected to associated and corresponding bias voltages VB₂ to VB_N.

30. The multiple-MOSFET stack circuit of claim 27, wherein each MOSFET M₂ to M_N has a corresponding and associated gate capacitor CG₂ to CG_N connected to the gate of each MOSFET M₂ to M_N, and also connected to a ground reference, and wherein an RF voltage across each MOSFET M₂ to M_N of the MOSFET transistor stack is determined by values of the associated and corresponding gate capacitors CG₂ to CG_N.

31. The multiple-MOSFET stack circuit of claim 30, wherein the DC and RF voltage across any one of the transistors M₂ to M_N of the transistor stack is controlled by the associated and corresponding bias voltages and gate capacitors, respectively, and wherein the DC and RF voltages divided across any one of the individual MOSFETs M₂ to M_N of the transistor stack are independently controlled.

32. The multiple-MOSFET stack circuit of claim 30, wherein the DC voltages across the transistors M₂ to M_N of the transistor stack are approximately equal.

33. The multiple-MOSFET stack circuit of claim 30, wherein the RF voltages across the transistors M₂ to M_N of the transistor stack are approximately equal.

34. The multiple-MOSFET stack circuit of claim 30, wherein the DC voltages across the transistors M₂ to M_N of the transistor stack are set to desired values.

35. The multiple-MOSFET stack circuit of claim 30, wherein the RF voltages across the transistors M₂ to M_N of the transistor stack are set to desired values.

36. The multiple-MOSFET stack circuit of claim 27, further comprising an integrated RF Power Amplifier (PA) circuit, the integrated RF PA circuit comprising:

a. an input node that is the input signal node of claim 27; and

b. a matching, coupling and filtering circuit connected to the drive output node.

37. A Class A, B, C, AB, or F RF PA comprising a circuit according to claim 27, wherein the multiple-MOSFET stack is configured as a primary amplifying device of the Class A, B, or C, AB, or F RF PA.

38. A quad mixer comprising a circuit according to claim 27.

39. An RF power management circuit comprising a circuit according to claim 27.