Full Chip Lithographic Mask Generation

• US 20170242333A1
• Filed: 02/23/2017
• Published: 08/24/2017
• Est. Priority Date: 02/23/2016
• Status: Active Grant

• Current Assignee: ASML US, LLC (ASML Holding NV)
• Original Assignee: XTAL, Inc.
• Inventors: Li, Jiangwei, Huang, Jihui, Zhao, Ke
• Granted Patent: US 10,146,124 B2
• Time in Patent Office: Days
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A method, an apparatus, and a non-transitory computer readable medium for full chip mask pattern generation include: generating, by a processor, an initial mask image from target polygons, performing, by the processor, a global image based full chip optimization of the initial mask image to generate new mask pattern polygons, wherein the global image based full chip optimization co-optimizes main feature polygons and SRAF image pixels, determining performance index information based on the global image based full chip optimization, wherein the performance index information comprises data for assisting a global polygon optimization, generating a mask based on the global polygon optimization of the new mask pattern polygons using the performance index information, and generating optimized mask patterns based on a localized polygon optimization of the mask.

Claims

1. A method for full integrated circuit (IC) mask pattern generation, comprising:

generating, by a processor, an initial mask image from target polygons;

performing, by the processor, a global image based full chip optimization of the initial mask image to generate new mask pattern polygons, wherein the global image based full chip optimization co-optimizes main feature polygons and SRAF image pixels;

determining performance index information based on the global image based full chip optimization, wherein the performance index information comprises data for assisting a global polygon optimization;

generating a mask based on the global polygon optimization of the new mask pattern polygons using the performance index information; and

generating optimized mask patterns based on a localized polygon optimization of the mask.

2. The method of claim 1, wherein the global polygon optimization comprises at least one iteration of a forward propagation and a backward propagation.

3. The method of claim 2, wherein the global polygon optimization comprises process conditions and a cost function for each process condition, wherein the process conditions comprise edge placement error and side lobe penalty.

4. The method of claim 3, wherein the cost function for the edge placement error minimizes polygon contour edge placement error in the mask.

5. The method of claim 3, wherein the cost function for the side lobe penalty prevents side lobe printing in the mask.

6. The method of claim 2, wherein the iteration of the forward propagation and the backward propagation provides updated variables for the global polygon optimization.

7. The method of claim 2, wherein the forward propagation comprises:

determining a symmetry group representative image for enforcing a symmetrical placement of SRAF polygons in the optimized mask patterns.

8. The method of claim 2, wherein the forward propagation comprises:

determining a mask image;

determining an aerial image associated with the mask image;

determining a resist image based on the aerial image;

determining a resist image intensity and a resist image intensity slopebased on the resist image; and

determining an edge placement error cost and a side lobe penalty costbased on the resist image.

9. The method of claim 2, wherein the backward propagation comprises:

receiving an edge placement error cost and a side lobe penalty cost from the forward propagation;

determining a cost gradient for edge propagation error and side lobe penalty for each pixel on a new mask pattern polygon; and

determining a variable update for the global polygon optimization based on the cost gradient.

10. The method of claim 1, wherein at least one of the global polygon optimization and localized polygon optimization comprises optical proximity correction (OPC) using process conditions on the new mask pattern polygons, wherein the new mask pattern polygons are fully dissected.

11. The method of claim 10, further comprising:

dissecting the new mask pattern polygons using a model based dissection technique.

12. The method of claim 1, wherein the global image based full chip optimization comprises a dissectionless based optimization.

13. The method of claim 1, wherein the global image based full chip optimization is based on an inverse lithographic technology (ILT) technique.

14. The method of claim 1, wherein the performance index information comprises parameters for hotspots identified during the global image based full chip optimization, wherein the parameters comprise at least one of an edge placement error, a process window metric, a mask error enhancement factor, and an image log slope value.

15. The method of claim 1, wherein the new mask pattern polygons are dissected to comprise main polygons and subresolution assist feature (SRAF) polygons.

16. The method of claim 1, wherein the processor comprises a central processing unit (CPU) and a graphics processing unit (GPU).

17. An apparatus for full chip mask pattern generation, comprising:

a memory; and

a processor configured to execute instructions stored in the memory to;

generate an initial mask image from target polygons;

perform a global image based full chip optimization of the initial mask image to generate new mask pattern polygons, wherein the global image based full chip optimization co-optimizes main feature polygons and SRAF image pixels;

determine performance index information based on the global image based full chip optimization, wherein the performance index information comprises data for assisting a global polygon optimization;

generate a mask based on the global polygon optimization of the new mask pattern polygons using the performance index information; and

generate optimized mask patterns based on a localized polygon optimization of the mask.

18. The apparatus of claim 17, wherein the global polygon optimization comprises at least one iteration of a forward propagation and a backward propagation.

19. The apparatus of claim 17, wherein the performance index information comprises parameters for hotspots identified during the global image based full chip optimization, wherein the parameters comprise at least one of an edge placement error, a process window metric, a mask error enhancement factor, and an image log slope value.

20. A non-transitory computer readable medium having stored thereon executable instructions for causing a processor to perform instructions to:

generate an initial mask image from target polygons;

perform a global image based full chip optimization of the initial mask image;

store performance index information produced by the global image based full chip optimization to generate new mask pattern polygons, wherein the global image based full chip optimization co-optimizes main feature polygons and SRAF image pixels;

generate a mask based on a global polygon optimization of the new mask pattern polygons using the performance index information; and

generate optimized mask patterns based on a localized polygon optimization of the mask.