METHODS AND SYSTEMS FOR TRANSITIONING TO AND FROM DIFFERENT STORAGE DEVICE POWER STATES USING HOST MEMORY BUFFER (HMB)

• US 20170242606A1
• Filed: 02/19/2016
• Published: 08/24/2017
• Est. Priority Date: 02/19/2016
• Status: Abandoned Application

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Vlaiko, Julian, Hahn, Judah Gamliel, Zagalsky, Yevgeny
• Application Number:
  US15/047,713
• Publication Number:
  US 20170242606A1
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The subject matter described herein includes methods, systems, and computer readable media for transitioning to and from storage device low power states using a host memory buffer (HMB). One storage device includes a non-volatile memory. A device controller controls access to the non-volatile memory. A host memory buffer (HMB)-assisted power state transition module operatively associated with the device controller stores storage device state information in a host memory buffer (HMB) in memory of host device separate from the storage device prior to the storage device entering a lower power state and uses the state information stored in the HMB to transition the storage device from the lower power state to a higher power state.

Claims

1. A storage device comprising:

non-volatile memory;

a device controller for controlling access to the non-volatile memory; and

a host memory buffer (HMB)-assisted power state transition module operatively associated with the device controller for storing storage device state information in a host memory buffer (HMB) in memory of host device separate from the storage device prior to the storage device entering a lower power state and for using the state information stored in the HMB to transition the storage device from the lower power state to a higher power state.

2. The storage device of claim 1 wherein the HMB-assisted power state transition module is configured to store data integrity check information for the state information stored in the HMB and address information for the state information stored in the HMB in an always on (AON) partition of static random access memory (SRAM) associated with the device controller.

3. The storage device of claim 2 wherein the HMB-assisted power state transition module is configured to use the address information to access the state information stored in the HMB and the data integrity check information to check the integrity of the state information stored in the HMB.

4. The storage device of claim 3 wherein the HMB-assisted power state transition module is configured to transition to the higher power state using state information retrieved from the non-volatile memory in response to a failure of the data integrity check.

5. The storage device of claim 3 wherein the HMB-assisted power state transition module is configured to transition the storage device to the higher power state using the state information retrieved from the HMB in response to passing of the data integrity check.

6. The storage device of claim 1 wherein the HMB-assisted power state transition module is configured to store data integrity check and address information for the state information stored in the HMB in the HMB and to retrieve the state information from the HMB and verify its integrity using the address and data integrity information stored in the HMB.

7. The storage device of claim 1 wherein the HMB-assisted power state transition module is configured to receive, via a register write from the host, an address in the HMB where the state information is stored and to use the address to retrieve the state information from the HMB.

8. The storage device of claim 7 wherein the register write includes a peripheral control interface express (PCIe) register write.

9. The storage device of claim 1 comprising dynamic random access memory (DRAM) located on the storage device, wherein the HMB-assisted power state transition module stores at least a portion of the storage device state information stored in the DRAM in the HMB prior to the storage device transitioning to the lower power state.

10. The storage device of claim 1 comprising a power management controller, wherein the HMB-assisted power state transition module is configured to store data integrity check information for the state information stored in the HMB and address information for the state information stored in the HMB in the power management controller.

11. The storage device of claim 1 wherein the HMB-assisted power state transition module is configured to store data error correcting and/or decryption key information prior to the storage device transitioning to the lower power state.

12. The storage device of claim 1 wherein the lower power state comprises one of a PS3 state, a PS4 state, and a runtime D3 (RTD3) state and wherein the higher power state comprises a PS0 state.

13. A method comprising:

in a storage device including nonvolatile memory and device controller for controlling access to the non-volatile memory;

storing storage device state information in a host memory buffer (HMB) in memory of a host device separate from the storage device prior to the storage device entering a lower power state; and

using the state information stored in the HMB to transition the storage device from the lower power state to a higher power state.

14. The method of claim 13 comprising storing data integrity check information for the state information stored in the HMB and address information for the state information stored in the HMB in an always on (AON) partition of static random access memory (SRAM) associated with the device controller.

15. The method of claim 14 comprising using the address information to access the state information stored in the HMB and the data integrity check information to check the integrity of the state information stored in the HMB.

16. The method of claim 15 comprising transitioning to the higher power state using state information retrieved from the non-volatile memory in response to a failure of the data integrity check.

17. The method of claim 15 comprising transitioning the storage device to the higher power state using the state information retrieved from the HMB in response to passing of the data integrity check.

18. The method of claim 13 comprising storing data integrity check and address information for the state information stored in the HMB in the HMB and retrieving the state information from the HMB using the address information and data integrity information stored in the HMB.

19. The method of claim 13 comprising receiving via a register write from the host, an address in the HMB where the state information is stored and using the address to retrieve the state information from the HMB.

20. The method of claim 19 wherein the register write includes a peripheral control interface express (PCIe) register write.

21. The method of claim 13 comprising providing dynamic random access memory (DRAM) located on the storage device, and wherein storing the storage device state information in the HMB comprises storing at least a portion of the storage device state information stored in the DRAM in the HMB prior to the storage device transitioning to the lower power state.

22. The method of claim 13 wherein the lower power state comprises one of a PS3 state, a PS4 state, and a runtime D3 (RTD3) state and wherein the higher power state comprises a PS0 state.

23. The method of claim 13 comprising storing data integrity check information for the state information stored in the HMB and address information for the state information stored in the HMB in a power management controller.

24. The method of claim 13 comprising storing data error correcting and/or decryption key information prior to the storage device transitioning to the lower power state.

25. A non-transitory computer readable medium having stored thereon executable instructions that when executed by the processor of a computer control the computer to perform steps comprising:

in a storage device including nonvolatile memory and device controller for controlling access to the non-volatile memory;

storing storage device state information in a host memory buffer (HMB) in memory of a host device separate from the storage device prior to the storage device entering a lower power state; and

using the state information stored in the HMB to transition the storage device from the lower power state to a higher power state.