WORD LINE DECODER CIRCUITRY UNDER A THREE-DIMENSIONAL MEMORY ARRAY

• US 20170243650A1
• Filed: 02/18/2016
• Published: 08/24/2017
• Est. Priority Date: 02/18/2016
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: OGAWA, Hiroyuki, TOYAMA, Fumiaki, ARIKI, Takuya
• Granted Patent: US 9,721,663 B1
• Time in Patent Office: Days
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

The total chip area for a three-dimensional memory device can be reduced employing a design layout in which the word line decoder circuitry is formed underneath an array of memory stack structures. The interconnection between the word lines and the word line decoder circuitry can be provided by forming discrete word line contact via structures. The discrete word line contact via structures can be formed by employing multiple sets of etch masks with overlapping opening areas and employed to etch a different number of pairs of insulating layers and electrically conductive layers, thereby obviating the need to form staircase regions having stepped surfaces. Sets of at least one conductive interconnection structure can be employed to provide vertical electrical connection to the word line decoder circuitry. Bit line drivers can also be formed underneath the array of memory stack structures to provide greater areal efficiency.

Claims

1. A memory device, comprising:

an alternating stack of insulating layers and electrically conductive layers located over a substrate;

an array of memory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises charge storage regions and a vertical semiconductor channel, and the electrically conductive layers comprise word lines for the memory stack structures;

a word line decoder circuitry including switches for activating a respective word line for the memory stack structures, and located underneath the array of memory stack structures and above the substrate;

a word line vertical interconnection region including multiple sets of at least one conductive interconnection structure, each set of at least one conductive interconnection structure electrically contacting a node of a respective device in the word line decoder circuitry;

bit lines electrically connected to the vertical semiconductor channels through respective drain regions and extending over the array of memory stack structures;

upper-interconnect-level word line connectors extending parallel to the bit lines over a portion of the array of memory stack structures, and electrically connecting a respective set of at least one conductive interconnection structure to the electrically conductive layers; and

at least one element selected from;

a first element of word line contact via structures contacting a respective electrically conductive layer and extending above the alternating stack and contacting a respective upper-interconnect-level word line connector;

a second element of a combination of at least one dielectric material layer overlying the word line decoder circuitry, and a semiconductor material layer overlying the at least one dielectric material layer and underlying the alternating stack; and

a third element of a bit line decoder circuitry including switches for activating a respective bit line for the memory stack structures, located underneath the array of memory stack structures and above the substrate and adjacent to the word line decoder circuitry, and having an areal overlap with the area of the array of memory stack structures in the plan view.

2. The memory device of claim 1, wherein the memory device comprises the first element.

3. The memory device of claim 2, wherein the node of the respective device in the word line decoder circuitry is selected from a source region of a field effect transistor, a drain region of a transistor, and a gate electrode of a field effect transistor.

4. The memory device of claim 2, wherein a set among the sets of at least one conductive interconnection structure comprises:

a stack level connector via structure extending from above a horizontal plane including a top surface of the alternating stack to another horizontal plane including a bottom surface of the alternating stack;

at least one connector metal line underlying the alternating stack; and

at least one connector via structure underlying the alternating stack.

5. The memory device of claim 1, wherein the memory device comprises the second element.

6. The memory device of claim 5, wherein the semiconductor material layer comprises horizontal semiconductor channels adjoined to the vertical semiconductor channels of the memory stack structures.

7. The memory device of claim 5, wherein the array of memory stack structures comprises multiple blocks of memory stack structures that are laterally spaced apart from one another by through-stack contact via structures extending through the alternating stack to a top surface of the semiconductor material layer.

8. The memory device of claim 7, wherein electrical connection between the word lines and the word line decoder circuitry comprises word line contact via structures contacting a respective electrically conductive layer from above and located between a respective neighboring pair of through-stack contact via structures.

9. The memory device of claim 7, wherein:

each block of memory stack structures comprises a plurality of clusters of memory stack structures laterally spaced by word line contact via structures contacting a respective electrically conductive layer from above; and

the plurality of clusters of memory stack structures are in a one-dimensional array extending along a horizontal direction parallel to a lengthwise direction of the through-stack contact via structures.

10. The memory device of claim 9, further comprising at least one feature selected from:

a first feature that each word line contact via structure extending through a same block of memory stack structures contacts a different electrically conductive layer in the alternating stack_l and

a second feature that wherein the word line contact via structures extending through a same block of memory stack structures are arranged as a one-dimensional array extending along a horizontal direction parallel to a lengthwise direction of the through-stack contact via structures in a Wan view.

12. The memory device of claim 1, wherein the memory device comprises the third element.

13. The memory device of claim 12, wherein:

the bit line decoder circuitry has a first rectangular area;

the word line decoder circuitry has a second rectangular area; and

a lengthwise direction of the first rectangular area and a lengthwise direction of the second rectangular area are along a same horizontal direction.

14. The memory device of claim 12, wherein:

the array of memory stack structures comprises multiple blocks of memory stack structures that are laterally spaced apart by through-stack contact via structures and laterally extending along a lengthwise direction;

vertical electrical connection between the word line decoder circuitry and the electrically conductive layers is provided in a first rectangular region that is laterally offset from an area of the array of memory stack structures and extends along the lengthwise direction; and

vertical electrical connection between the bit line decoder circuitry and the bit lines of the memory stack structures is provided in a second rectangular region that is laterally offset from the area of the memory stack structures and extends along the lengthwise direction.

15. The memory device of claim 14, further comprising:

an additional array of memory stack structures comprising additional multiple blocks of memory stack structures and laterally spaced from the array of memory stack structures by the second rectangular region; and

a third rectangular region including vertical connection between an additional word line decoder circuitry including switches for activating a respective word line for the memory stack structures of the additional array of memory stack structures, located underneath the additional array of memory stack structures and above the substrate, and having an areal overlap with an area of the additional array of memory stack structures in the plan view,

wherein the second rectangular region comprises vertical electrical connection between bit lines of the additional array of memory stack structures and the bit line decoder circuitry.

16. The memory device of claim 14, wherein the memory device comprises a periodic repetition of multiple instances of the array of memory stack structures, the first rectangular region, and the second rectangular region.

17. The memory device of claim 1, wherein the memory device comprises the first feature.

18. The memory device of claim 1, wherein the memory device comprises the second feature the word line decoder circuitry has an areal overlap with an area of the array of memory stack structures in a plan view.

19. The memory device of claim 1, wherein the memory device comprises the third feature.

20. The memory device of claim 1, wherein the memory device comprises the fourth feature.

11. (canceled)

21. A method of forming a memory device, comprising:

forming a word line decoder circuitry over a substrate;

forming a memory cell array over the word line decoder circuitry, wherein;

the memory cell array includes an alternating stack of insulating layers and electrically conductive layers and an array of memory stack structures extending through the alternating stack,

each of the memory stack structures comprises charge storage regions and a vertical semiconductor channel,

the electrically conductive layers comprise word lines for the memory stack structures, and

the word line decoder circuitry includes switches for activating a respective word line for the memory stack structures;

forming a word line vertical interconnection region including multiple sets of at least one conductive interconnection structure, each set of at least one conductive interconnection structure contacting a node of a respective device in the word line decoder circuitry;

forming bit lines electrically connected to the vertical semiconductor channels through respective drain regions and extending over the array of memory stack structures; and

forming upper-interconnect-level word line connectors extending parallel to the bit lines over a portion of the array of memory stack structures, and electrically connecting a respective set of at least one conductive interconnection structure to the electrically conductive layers,

wherein the method comprises at least one feature selected from;

a first feature of performing a step of forming word line contact via structures contacting a respective electrically conductive layer and extending above the alternating stack, wherein the upper-interconnect-level word line connectors are formed on respective word line contact via structures;

a second feature of performing a step of forming at least one dielectric material layer overlying the word line decoder circuitry, and forming a semiconductor material layer over the at least one dielectric material layer, wherein the semiconductor material layer comprises horizontal semiconductor channels adjoined to the vertical semiconductor channels of the memory stack structures;

a third feature of performing a step of forming through-stack contact via structures through the alternating stack, wherein the array of memory stack structures comprises multiple blocks of memory stack structures that are laterally spaced apart from one another by the through-stack contact via structures;

a fourth feature of performing a step of forming a bit line decoder circuitry over the substrate, wherein the bit line decoder circuitry includes switches for activating a respective bit line for the memory stack structures, located underneath the array of memory stack structures and above the substrate and adjacent to the word line decoder circuitry, and having an areal overlap with the area of the array of memory stack structures in the plan view;

a fifth feature of performing a step of etching a set of word line connection holes employing multiple sets of processing steps, each set of processing steps comprising;

a first step of applying a photoresist layer,

a second step of lithographically patterning the photoresist layer with a respective set of openings,

a third step of etching through a respective number of pairs of electrically conductive layers and insulating layers in areas underlying the respective set of openings from the second step, and

a fourth step of removing the photoresist laver; and

a sixth feature that;

the array of memory stack structures comprises memory elements of a vertical NAND device,

the electrically conductive layers comprise, or are electrically connected to, a respective word line of the vertical NAND device,

the substrate comprises a silicon substrate,

the vertical NAND device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate,

at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings,

the silicon substrate contains an integrated circuit comprising the word line driver circuit and a bit line driver circuit for the memory device, and

the array of monolithic three-dimensional NAND strings comprises;

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate,

a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels, and

a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.

22. The method of claim 21, wherein the method comprises the first feature.

23. The method of claim 22, wherein a set among the sets of at least one conductive interconnection structure comprises:

a stack level connector via structure extending from above a horizontal plane including a top surface of the alternating stack to another horizontal plane including a bottom surface of the alternating stack;

at least one connector metal line underlying the alternating stack; and

at least one connector via structure underlying the alternating stack.

24. The method of claim 21, wherein the method comprises the second feature.

25. The method of claim 21, wherein the method comprises the third feature.

26. The method of claim 25, further comprising forming word line contact via structures extending through an upper portion of the alternating stack to a respective electrically conductive layer, wherein:

each block of memory stack structures comprises a plurality of clusters of memory stack structures laterally spaced by the word line contact via structures; and

the plurality of clusters of memory stack structures are in a one-dimensional array extending along a horizontal direction parallel to a lengthwise direction of the through-stack contact via structures.

27. The method of claim 21, wherein the method comprises the fourth feature.

28. The method of claim 27, wherein:

the array of memory stack structures comprises multiple blocks of memory stack structures that are laterally spaced apart by through-stack contact via structures and laterally extending along a lengthwise direction;

vertical electrical connection between the word line decoder circuitry and the electrically conductive layers is provided in a first rectangular region that is laterally offset from an area of the array of memory stack structures and extends along the lengthwise direction; and

vertical electrical connection between the bit line decoder circuitry and the bit lines of the memory stack structures is provided in a second rectangular region that is laterally offset from the area of the memory stack structures and extends along the lengthwise direction.

29. The method of claim 28, further comprising:

forming an additional array of memory stack structures comprising additional multiple blocks of memory stack structures and laterally spaced from the array of memory stack structures by the second rectangular region; and

forming a third rectangular region including vertical connection between an additional word line decoder circuitry including switches for activating a respective word line for the memory stack structures of the additional array of memory stack structures, located underneath the additional array of memory stack structures and above the substrate, and having an areal overlap with an area of the additional array of memory stack structures in the plan view,

wherein the second rectangular region comprises vertical electrical connection between an additional bit line decoder circuitry for the additional array of memory stack structures and the bit lines of additional array of memory stack structures.

30. The method of claim 28, wherein the memory device comprises a periodic repetition of multiple instances of the array of memory stack structures, the first rectangular region, and the second rectangular region.

31. The method of claim 21, wherein the method comprises the fifth feature.

32. The method of claim 31, wherein:

the respective number of pairs of electrically conductive layers and insulating layers differs from set to set among the multiple sets of processing steps; and

a predominant subset of word line connection holes is formed employing at least two instances of the third step.

33. The method of claim 21, wherein the method comprises the sixth feature.

34. A memory device, comprising:

an alternating stack of insulating layers and electrically conductive layers located over a substrate;

an array of memory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises charge storage regions and a vertical semiconductor channel, and the electrically conductive layers comprise word lines for the memory stack structures;

a word line decoder circuitry including switches for activating a respective word line for the memory stack structures, and located underneath the array of memory stack structures and above the substrate;

a word line vertical interconnection region including multiple sets of at least one conductive interconnection structure, each set of at least one conductive interconnection structure electrically contacting a node of a respective device in the word line decoder circuitry;

bit lines electrically connected to the vertical semiconductor channels through respective drain regions and extending over the array of memory stack structures; and

upper-interconnect-level word line connectors extending parallel to the bit lines over a portion of the array of memory stack structures, and electrically connecting a respective set of at least one conductive interconnection structure to the electrically conductive layers, wherein the memory device comprises at least one feature selected from;

a first feature that the array of memory stack structures comprises multiple blocks of memory stack structures, and each electrically conductive layer includes a respective number of holes therethrough within each block of memory stack structures, wherein the respective number of holes for a given electrically conductive layer is the same as a total number of electrically conductive layers underlying the given electrically conductive layer;

a second feature that wherein the word line decoder circuitry has an areal overlap with an area of the array of memory stack structures in a plan view;

a third feature that the array of memory stack structures includes blocks of memory stack structures having a rectangular shape and laterally bounded by a pair of through-stack contact via structures, and the upper-interconnect-level word line connectors extend along a direction perpendicular to a lengthwise direction of the rectangular shapes of the blocks of memory stack structures; and

a fourth feature that;

the array of memory stack structures comprises memory elements of a vertical NAND device,

the electrically conductive layers comprise, or are electrically connected to, a respective word line of the vertical NAND device,

the substrate comprises a silicon substrate,

the vertical NAND device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate,

at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings,

the silicon substrate contains an integrated circuit comprising the word line driver circuit and a bit line driver circuit for the memory device, and

the array of monolithic three-dimensional NAND strings comprises;

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate,

a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels, and

a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.