WORD LINE DECODER CIRCUITRY UNDER A THREE-DIMENSIONAL MEMORY ARRAY
First Claim
1. A memory device, comprising:
- an alternating stack of insulating layers and electrically conductive layers located over a substrate;
an array of memory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises charge storage regions and a vertical semiconductor channel, and the electrically conductive layers comprise word lines for the memory stack structures;
a word line decoder circuitry including switches for activating a respective word line for the memory stack structures, and located underneath the array of memory stack structures and above the substrate;
a word line vertical interconnection region including multiple sets of at least one conductive interconnection structure, each set of at least one conductive interconnection structure electrically contacting a node of a respective device in the word line decoder circuitry;
bit lines electrically connected to the vertical semiconductor channels through respective drain regions and extending over the array of memory stack structures;
upper-interconnect-level word line connectors extending parallel to the bit lines over a portion of the array of memory stack structures, and electrically connecting a respective set of at least one conductive interconnection structure to the electrically conductive layers; and
at least one element selected from;
a first element of word line contact via structures contacting a respective electrically conductive layer and extending above the alternating stack and contacting a respective upper-interconnect-level word line connector;
a second element of a combination of at least one dielectric material layer overlying the word line decoder circuitry, and a semiconductor material layer overlying the at least one dielectric material layer and underlying the alternating stack; and
a third element of a bit line decoder circuitry including switches for activating a respective bit line for the memory stack structures, located underneath the array of memory stack structures and above the substrate and adjacent to the word line decoder circuitry, and having an areal overlap with the area of the array of memory stack structures in the plan view.
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Accused Products
Abstract
The total chip area for a three-dimensional memory device can be reduced employing a design layout in which the word line decoder circuitry is formed underneath an array of memory stack structures. The interconnection between the word lines and the word line decoder circuitry can be provided by forming discrete word line contact via structures. The discrete word line contact via structures can be formed by employing multiple sets of etch masks with overlapping opening areas and employed to etch a different number of pairs of insulating layers and electrically conductive layers, thereby obviating the need to form staircase regions having stepped surfaces. Sets of at least one conductive interconnection structure can be employed to provide vertical electrical connection to the word line decoder circuitry. Bit line drivers can also be formed underneath the array of memory stack structures to provide greater areal efficiency.
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Citations
34 Claims
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1. A memory device, comprising:
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an alternating stack of insulating layers and electrically conductive layers located over a substrate; an array of memory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises charge storage regions and a vertical semiconductor channel, and the electrically conductive layers comprise word lines for the memory stack structures; a word line decoder circuitry including switches for activating a respective word line for the memory stack structures, and located underneath the array of memory stack structures and above the substrate; a word line vertical interconnection region including multiple sets of at least one conductive interconnection structure, each set of at least one conductive interconnection structure electrically contacting a node of a respective device in the word line decoder circuitry; bit lines electrically connected to the vertical semiconductor channels through respective drain regions and extending over the array of memory stack structures; upper-interconnect-level word line connectors extending parallel to the bit lines over a portion of the array of memory stack structures, and electrically connecting a respective set of at least one conductive interconnection structure to the electrically conductive layers; and at least one element selected from; a first element of word line contact via structures contacting a respective electrically conductive layer and extending above the alternating stack and contacting a respective upper-interconnect-level word line connector; a second element of a combination of at least one dielectric material layer overlying the word line decoder circuitry, and a semiconductor material layer overlying the at least one dielectric material layer and underlying the alternating stack; and a third element of a bit line decoder circuitry including switches for activating a respective bit line for the memory stack structures, located underneath the array of memory stack structures and above the substrate and adjacent to the word line decoder circuitry, and having an areal overlap with the area of the array of memory stack structures in the plan view. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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11. (canceled)
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21. A method of forming a memory device, comprising:
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forming a word line decoder circuitry over a substrate; forming a memory cell array over the word line decoder circuitry, wherein; the memory cell array includes an alternating stack of insulating layers and electrically conductive layers and an array of memory stack structures extending through the alternating stack, each of the memory stack structures comprises charge storage regions and a vertical semiconductor channel, the electrically conductive layers comprise word lines for the memory stack structures, and the word line decoder circuitry includes switches for activating a respective word line for the memory stack structures; forming a word line vertical interconnection region including multiple sets of at least one conductive interconnection structure, each set of at least one conductive interconnection structure contacting a node of a respective device in the word line decoder circuitry; forming bit lines electrically connected to the vertical semiconductor channels through respective drain regions and extending over the array of memory stack structures; and forming upper-interconnect-level word line connectors extending parallel to the bit lines over a portion of the array of memory stack structures, and electrically connecting a respective set of at least one conductive interconnection structure to the electrically conductive layers, wherein the method comprises at least one feature selected from; a first feature of performing a step of forming word line contact via structures contacting a respective electrically conductive layer and extending above the alternating stack, wherein the upper-interconnect-level word line connectors are formed on respective word line contact via structures; a second feature of performing a step of forming at least one dielectric material layer overlying the word line decoder circuitry, and forming a semiconductor material layer over the at least one dielectric material layer, wherein the semiconductor material layer comprises horizontal semiconductor channels adjoined to the vertical semiconductor channels of the memory stack structures; a third feature of performing a step of forming through-stack contact via structures through the alternating stack, wherein the array of memory stack structures comprises multiple blocks of memory stack structures that are laterally spaced apart from one another by the through-stack contact via structures; a fourth feature of performing a step of forming a bit line decoder circuitry over the substrate, wherein the bit line decoder circuitry includes switches for activating a respective bit line for the memory stack structures, located underneath the array of memory stack structures and above the substrate and adjacent to the word line decoder circuitry, and having an areal overlap with the area of the array of memory stack structures in the plan view; a fifth feature of performing a step of etching a set of word line connection holes employing multiple sets of processing steps, each set of processing steps comprising; a first step of applying a photoresist layer, a second step of lithographically patterning the photoresist layer with a respective set of openings, a third step of etching through a respective number of pairs of electrically conductive layers and insulating layers in areas underlying the respective set of openings from the second step, and a fourth step of removing the photoresist laver; and a sixth feature that; the array of memory stack structures comprises memory elements of a vertical NAND device, the electrically conductive layers comprise, or are electrically connected to, a respective word line of the vertical NAND device, the substrate comprises a silicon substrate, the vertical NAND device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate, at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings, the silicon substrate contains an integrated circuit comprising the word line driver circuit and a bit line driver circuit for the memory device, and the array of monolithic three-dimensional NAND strings comprises; a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate, a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels, and a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33)
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34. A memory device, comprising:
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an alternating stack of insulating layers and electrically conductive layers located over a substrate; an array of memory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises charge storage regions and a vertical semiconductor channel, and the electrically conductive layers comprise word lines for the memory stack structures; a word line decoder circuitry including switches for activating a respective word line for the memory stack structures, and located underneath the array of memory stack structures and above the substrate; a word line vertical interconnection region including multiple sets of at least one conductive interconnection structure, each set of at least one conductive interconnection structure electrically contacting a node of a respective device in the word line decoder circuitry; bit lines electrically connected to the vertical semiconductor channels through respective drain regions and extending over the array of memory stack structures; and upper-interconnect-level word line connectors extending parallel to the bit lines over a portion of the array of memory stack structures, and electrically connecting a respective set of at least one conductive interconnection structure to the electrically conductive layers, wherein the memory device comprises at least one feature selected from; a first feature that the array of memory stack structures comprises multiple blocks of memory stack structures, and each electrically conductive layer includes a respective number of holes therethrough within each block of memory stack structures, wherein the respective number of holes for a given electrically conductive layer is the same as a total number of electrically conductive layers underlying the given electrically conductive layer; a second feature that wherein the word line decoder circuitry has an areal overlap with an area of the array of memory stack structures in a plan view; a third feature that the array of memory stack structures includes blocks of memory stack structures having a rectangular shape and laterally bounded by a pair of through-stack contact via structures, and the upper-interconnect-level word line connectors extend along a direction perpendicular to a lengthwise direction of the rectangular shapes of the blocks of memory stack structures; and a fourth feature that; the array of memory stack structures comprises memory elements of a vertical NAND device, the electrically conductive layers comprise, or are electrically connected to, a respective word line of the vertical NAND device, the substrate comprises a silicon substrate, the vertical NAND device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate, at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings, the silicon substrate contains an integrated circuit comprising the word line driver circuit and a bit line driver circuit for the memory device, and the array of monolithic three-dimensional NAND strings comprises; a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate, a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels, and a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.
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Specification