Powermap Optimized Thermally Aware 3D Chip Package

• US 20170243806A1
• Filed: 02/19/2016
• Published: 08/24/2017
• Est. Priority Date: 02/19/2016
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Iyengar, Madhu Krishnan, Kang, Teck-Gyu, Malone, Christopher Gregory, Jouppi, Norman Paul
• Granted Patent: US 10,032,695 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 2224/29193 with a principal constituent of the material being a solid not provided for in groups H01L2224/291 - H01L2224/29191, e.g. allotropes of carbon, fullerene, graphite, carbon-nanotubes, diamond
• CPC Class Codes: H01L 2224/29247 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/29309 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/29393 with a principal constituent of the material being a solid not provided for in groups H01L2224/293 - H01L2224/29391, e.g. allotropes of carbon, fullerene, graphite, carbon-nanotubes, diamond
• CPC Class Codes: H01L 23/04 characterised by the shape of the container or parts, e.g. caps, walls
• CPC Class Codes: H01L 23/3675 characterised by the shape of the housing
• CPC Class Codes: H01L 23/373 Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
• CPC Class Codes: H01L 23/3732 Diamonds
• CPC Class Codes: H01L 23/3736 Metallic materials H01L23/3732, H01L23/3733, H01L23/3735, H01L23/3737, H01L23/3738 take precedence
• CPC Class Codes: H01L 23/3737 Organic materials with or without a thermoconductive filler
• CPC Class Codes: H01L 23/44 the complete device being wholly immersed in a fluid other than air H01L23/427 takes precedence
• CPC Class Codes: H01L 23/473 by flowing liquids H01L23/4332, H01L23/4338 take precedence
• CPC Class Codes: H01L 23/498 Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers shape of the substrate H01L23/13
• CPC Class Codes: H01L 24/00 Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/1431 Logic devices
• CPC Class Codes: H01L 2924/1433 Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/1436 : Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/16151 : Cap comprising an aperture, e.g. for pressure control, encapsulation
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Abstract

A semiconductor package includes a substrate, an integrated circuit disposed on the substrate, a memory support disposed on the integrated circuit, stacked memory disposed on the memory support and in communication with the integrated circuit, and a lid connected to the substrate. The integrated circuit has a low power region and a high power region. The memory support is disposed on the low power region of the integrated circuit and is configured to allow a flow of fluid therethrough to conduct heat away from the low power region of the integrated circuit. The lid defines a first port, a second port, and a lid volume fluidly connecting the first port and the second port. The lid volume is configured to house the integrated circuit, the memory support, and the stacked memory, while directing the flow of fluid to flow over the integrated circuit, the memory support, and the stacked memory.

Claims

1. A semiconductor package comprising:

a substrate;

an integrated circuit disposed on the substrate, the integrated circuit having a low power region and a high power region;

a memory support disposed on the low power region of the integrated circuit, the memory support configured to allow a flow of fluid therethrough to conduct heat away from the low power region of the integrated circuit;

stacked memory disposed on the memory support and in communication with the integrated circuit; and

a lid connected to the substrate and defining a first port, a second port, and a lid volume fluidly connecting the first port and the second port, the lid volume configured to house the integrated circuit, the memory support, and the stacked memory, while directing the flow of fluid to flow over the integrated circuit, the memory support, and the stacked memory.

2. The semiconductor package of claim 1, further comprising a heat sink disposed on the high power region of the integrated circuit, the lid volume configured to house the heat sink while directing the flow of fluid to flow over the heat sink, the heat sink having a plurality of fins.

3. The semiconductor package of claim 1, further comprising a heat conductive material disposed on the high power region of the integrated circuit, the lid volume configured to house the heat conductive material while directing the flow of fluid to flow over the heat conductive material.

4. The semiconductor package of claim 3, wherein the heat conductive material comprises diamond and/or a composite of Copper and:

Carbon nanotubes;

or

Indium.

5. The semiconductor package of claim 1, further comprising a heat sink disposed on a heat conductive material, the heat conductive material disposed on the high power region of the integrated circuit, the lid volume configured to house the heat sink while directing the flow of fluid to flow over the heat sink, the heat sink having a plurality of fins.

6. The semiconductor package of claim 1, wherein the low power region and the high power region do not overlap.

7. The semiconductor package of claim 1, wherein the memory support comprises a porous material.

9. The semiconductor package of claim 1, further comprising an interposer disposed on the integrated circuit.

10. The semiconductor package of claim 1, wherein the memory support is configured to electrically connect the memory and the integrated circuit.

8. The semiconductor package of claim 8, wherein the porous material defines regularly spaced pores.

11. A method comprising:

receiving a flow of fluid; and

directing the flow of fluid over surfaces of a semiconductor package comprising stacked memory and an integrated circuit,

wherein the integrated circuit has a low power region and a high power region, the stacked memory supported by a memory support on the low power region of the integrated circuit, the memory support directing the flow of fluid to conduct heat away from the low power region and the high power region of the integrated circuit.

12. The method of claim 11, further comprising directing the flow of fluid with a lid defining a first port, a second port, and a lid volume fluidly connecting the first port and the second port, the lid volume configured to house the integrated circuit, the memory support, and the stacked memory, while directing the flow of fluid to flow over the integrated circuit, the memory support, and the stacked memory.

13. The method of claim 12, wherein the semiconductor package further comprises a heat sink disposed on the high power region of the integrated circuit, the lid volume configured to house the heat sink while directing the flow of fluid to flow over the heat sink, the heat sink having a plurality of fins.

14. The method of claim 12, wherein the semiconductor package further comprises a heat conductive material disposed on the high power region of the integrated circuit, the lid volume configured to house the heat conductive material while directing the flow of fluid to flow over the heat conductive material.

15. The method of claim 14, wherein the heat conductive material comprises diamond and/or a composite of Copper and:

Carbon nanotubes;

or

Indium.

16. The method of claim 12, wherein the semiconductor package further comprises a heat sink disposed on a heat conductive material, the heat conductive material disposed on the high power region of the integrated circuit, the lid volume configured to house the heat sink while directing the flow of fluid to flow over the heat sink, the heat sink having a plurality of fins.

17. The method of claim 11, wherein the low power region and the high power region do not overlap.

18. The method of claim 11, wherein the memory support comprises a porous material.

19. The method of claim 18, wherein the porous material defines regularly spaced pores.

20. The method of claim 11, wherein the semiconductor package further comprises an interposer disposed on the integrated circuit.

21. The method of claim 11, wherein the memory support is configured to electrically connect the memory and the integrated circuit.