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SEMICONDUCTOR MEMORY DEVICE

  • US 20170243873A1
  • Filed: 09/19/2016
  • Published: 08/24/2017
  • Est. Priority Date: 02/22/2016
  • Status: Active Grant
First Claim
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1. A semiconductor memory device, comprising:

  • a stacked body including a plurality of control gate electrodes stacked upwardly of a substrate;

    a semiconductor layer extending along a first direction intersecting an upper surface of the substrate, the semiconductor layer facing the plurality of control gate electrodes; and

    a gate insulating layer provided between the control gate electrode and the semiconductor layer,the stacked body comprising;

    a first metal layer configuring the control gate electrode;

    a first barrier metal layer contacting an upper surface of the first metal layer;

    a first silicon nitride layer contacting an upper surface of the first barrier metal layer;

    a first inter-layer insulating layer contacting an upper surface of the first silicon nitride layer;

    a second barrier metal layer contacting a lower surface of the first metal layer;

    a second silicon nitride layer contacting a lower surface of the second barrier metal layer; and

    a second inter-layer insulating layer contacting a lower surface of the second silicon nitride layer.

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