SEMICONDUCTOR MEMORY DEVICE

• US 20170243873A1
• Filed: 09/19/2016
• Published: 08/24/2017
• Est. Priority Date: 02/22/2016
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: KOBAYASHI, Shigeki, KONAGAI, Satoshi, KONNO, Atsushi, YAMADA, Kenta, HIGUCHI, Masaaki, SHINGU, Masao, KITAZAKI, Soichiro, MIKAJIRI, Yoshimasa
• Granted Patent: US 10,121,797 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/28158 Making the insulator
• CPC Class Codes: H01L 21/28556 by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 28/00 Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor testing or measuring during manufacture H01L22/00; integration methods H01L21/70; integrated circuits H01L27/00; two-terminal components with a potential-jump or surface barrier H01L29/00; resistors in general H01C; inductors in general H01F; capacitors in general H01G
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/4234 Gate electrodes for transistors with charge trapping gate insulator
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

According to an embodiment, a semiconductor memory device comprises: a stacked body including control gate electrodes stacked upwardly of a substrate; a semiconductor layer facing the control gate electrodes; and a gate insulating layer provided between the control gate electrode and the semiconductor layer. The stacked body comprises: a first metal layer configuring the control gate electrode; a first barrier metal layer contacting an upper surface of this first metal layer; a first silicon nitride layer contacting an upper surface of this first barrier metal layer; a first inter-layer insulating layer contacting an upper surface of this first silicon nitride layer; a second barrier metal layer contacting a lower surface of the first metal layer; a second silicon nitride layer contacting a lower surface of this second barrier metal layer; and a second inter-layer insulating layer contacting a lower surface of this second silicon nitride layer.

Claims

1. A semiconductor memory device, comprising:

a stacked body including a plurality of control gate electrodes stacked upwardly of a substrate;

a semiconductor layer extending along a first direction intersecting an upper surface of the substrate, the semiconductor layer facing the plurality of control gate electrodes; and

a gate insulating layer provided between the control gate electrode and the semiconductor layer,

the stacked body comprising;

a first metal layer configuring the control gate electrode;

a first barrier metal layer contacting an upper surface of the first metal layer;

a first silicon nitride layer contacting an upper surface of the first barrier metal layer;

a first inter-layer insulating layer contacting an upper surface of the first silicon nitride layer;

a second barrier metal layer contacting a lower surface of the first metal layer;

a second silicon nitride layer contacting a lower surface of the second barrier metal layer; and

a second inter-layer insulating layer contacting a lower surface of the second silicon nitride layer.

2. The semiconductor memory device according to claim 1, further comprising

a third barrier metal layer formed integrally with the first barrier metal layer and the second barrier metal layer,

wherein the third barrier metal layer contacts side surfaces of the first metal layer and the gate insulating layer.

3. The semiconductor memory device according to claim 2, wherein

the first barrier metal layer, the second barrier metal layer, and the third barrier metal layer include at least one of titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), and tungsten nitride (WN).

4. The semiconductor memory device according to claim 2, wherein

a film thickness of the third barrier metal layer is larger than a film thickness of the first barrier metal layer and a film thickness of the second barrier metal layer.

5. The semiconductor memory device according to claim 2, further comprising

a fourth barrier metal layer and a fifth barrier metal layer that are formed integrally with the third barrier metal layer,

wherein the fourth barrier metal layer projects upwardly and contacts side surfaces of the first silicon nitride layer and the gate insulating layer,

the fifth barrier metal layer projects downwardly and contacts side surfaces of the second silicon nitride layer and the gate insulating layer, and

a film thickness of the third barrier metal layer is larger than a film thickness of the fourth barrier metal layer and a film thickness of the fifth barrier metal layer.

6. The semiconductor memory device according to claim 1, further comprising:

a third barrier metal layer formed integrally with the first barrier metal layer and the second barrier metal layer; and

a third silicon nitride layer formed integrally with the first silicon nitride layer and the second silicon nitride layer,

wherein the third barrier metal layer contacts side surfaces of the first metal layer and the third silicon nitride layer, and

the third silicon nitride layer contacts a side surface of the gate insulating layer.

7. The semiconductor memory device according to claim 6, wherein

the first barrier metal layer, the second barrier metal layer, and the third barrier metal layer include at least one of titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), and tungsten nitride (WN).

8. The semiconductor memory device according to claim 6, wherein

a film thickness of the third silicon nitride layer is 1.5 nm or more.

9. The semiconductor memory device according to claim 6, wherein

the semiconductor layer has a columnar or cylindrical shape.

10. The semiconductor memory device according to claim 1, wherein

the first metal layer comprises a contact part connected to a via contact wiring line,

the semiconductor memory device further comprising:

a sixth barrier metal layer contacting an upper surface of the contact part; and

a third inter-layer insulating layer positioned upwardly of the contact part,

wherein a gap or a part of the via contact wiring line is provided between an upper surface of the sixth barrier metal layer and a lower surface of the third inter-layer insulating layer.

11. The semiconductor memory device according to claim 1, wherein

the gate insulating layer

has a cylindrical shape extending along the first direction, is provided between a plurality of the control gate electrodes and the semiconductor layer,

and comprises:

a tunnel insulating layer covering a side surface of the semiconductor layer;

a charge accumulation layer covering a side surface of the tunnel insulating layer;

a first block insulating layer formed on a side surface of the charge accumulation layer and including the likes of silicon oxide (SiO₂); and

a second block insulating layer formed on a side surface of the first block insulating layer and configured from a high dielectric insulating layer.

12. The semiconductor memory device according to claim 11, wherein

the high dielectric insulating layer includes at least one of aluminum oxide (AlO_x) and hafnium oxide (HfO_x).

13. The semiconductor memory device according to claim 1, wherein

the first inter-layer insulating layer and the second inter-layer insulating layer include silicon oxide (SiO₂).

14. A semiconductor memory device, comprising:

a stacked body including a plurality of control gate electrodes stacked upwardly of a substrate;

a semiconductor layer having a columnar or cylindrical shape extending along a first direction intersecting an upper surface of the substrate, the semiconductor layer facing the plurality of control gate electrodes;

a charge accumulation layer provided between the semiconductor layer and the control gate electrode;

a high dielectric insulating layer provided between the charge accumulation layer and the control gate electrode; and

a silicon nitride layer provided between the high dielectric insulating layer and the control gate electrode,

the stacked body comprising;

a first metal layer configuring the control gate electrode; and

a barrier metal layer contacting an upper surface, lower surface, and side surface of the first metal layer, and

the silicon nitride layer contacting a side surface of the high dielectric insulating layer and a side surface of the barrier metal layer.

15. The semiconductor memory device according to claim 14, wherein

the barrier metal layer includes at least one of titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), and tungsten nitride (WN).

16. The semiconductor memory device according to claim 14, wherein

the high dielectric insulating layer includes at least one of aluminum oxide (AlO_x) and hafnium oxide (HfO_x).

17. The semiconductor memory device according to claim 14, wherein

the silicon nitride layer contacts an upper surface, lower surface, and side surface of the barrier metal layer, and

the high dielectric insulating layer contacts an upper surface, lower surface, and side surface of the silicon nitride layer.

18. The semiconductor memory device according to claim 14, wherein

the high dielectric insulating layer has a cylindrical shape extending along the first direction and is provided between a plurality of the control gate electrodes and the semiconductor layer.

19. The semiconductor memory device according to claim 14, wherein

a film thickness of the silicon nitride layer is 1.5 nm or more.