Semiconductor Device and Electronic Device

• US 20170243892A1
• Filed: 05/08/2017
• Published: 08/24/2017
• Est. Priority Date: 02/21/2014
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Umezaki, Atsushi
• Granted Patent: US 10,453,866 B2
• Time in Patent Office: Days
• CPC Class Codes: G02F 1/13306 Circuit arrangements or driving methods for the control of single liquid crystal cells G02F1/132, G02F1/133382 take precedence
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3674 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H03K 19/00346 Modifications for eliminating interference or parasitic voltages or currents

Abstract

To provide a novel shift register. Transistors 101 to 104 are provided. A first terminal of the transistor 101 is connected to a wiring 111 and a second terminal of the transistor 101 is connected to a wiring 112. A first terminal of the transistor 102 is connected to a wiring 113 and a second terminal of the transistor 102 is connected to the wiring 112. A first terminal of the transistor 103 is connected to the wiring 113 and a gate of the transistor 103 is connected to the wiring 111 or a wiring 119. A first terminal of the transistor 104 is connected to a second terminal of the transistor 103, a second terminal of the transistor 104 is connected to a gate of the transistor 101, and a gate of the transistor 104 is connected to a gate of the transistor 102.

Claims

1. (canceled)

2. A semiconductor device comprising:

a first transistor, a second transistor, a third transistor, and a fourth transistor; and

a first wiring and a second wiring,

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,

wherein the other of the source and the drain of the first transistor and a gate of the third transistor are electrically connected to the first wiring,

wherein a gate of the first transistor is electrically connected to one of a source and a drain of the fourth transistor,

wherein the other of the source and the drain of the second transistor and one of a source and a drain of the third transistor are electrically connected to the second wiring,

wherein a gate of the second transistor is electrically connected to a gate of the fourth transistor, and

wherein the other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the fourth transistor.

3. The semiconductor device according to claim 2, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor have the same conductivity type.

4. The semiconductor device according to claim 2, wherein a ratio of a channel width to a channel length of the fourth transistor is higher than a ratio of a channel width to a channel length of the third transistor.

5. The semiconductor device according to claim 2, wherein the third transistor comprises a first semiconductor layer and a first gate electrode,

wherein the fourth transistor comprises a second semiconductor layer and a second gate electrode, and

wherein an area where the second semiconductor layer and the second gate electrode overlap with each other is larger than an area where the first semiconductor layer and the first gate electrode overlap with each other.

6. The semiconductor device according to claim 2, wherein a channel formation region of at least one of the first transistor, the second transistor, the third transistor, and the fourth transistor comprises an oxide semiconductor.

7. The semiconductor device according to claim 2,

wherein the first wiring is configured to supply a clock signal to the other of the source and the drain of the first transistor and the gate of the third transistor, and

wherein the second wiring is configured to supply a voltage to the other of the source and the drain of the second transistor and the one of the source and the drain of the third transistor.

8. A semiconductor device comprising:

a first transistor, a second transistor, a third transistor, and a fourth transistor; and

a first wiring, a second wiring, and a third wiring,

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,

wherein the other of the source and the drain of the first transistor is electrically connected to the first wiring,

wherein a gate of the first transistor is electrically connected to one of a source and a drain of the fourth transistor,

wherein the other of the source and the drain of the second transistor and one of a source and a drain of the third transistor are electrically connected to the second wiring,

wherein a gate of the second transistor is electrically connected to a gate of the fourth transistor,

wherein the other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the fourth transistor,

wherein a gate of the third transistor is electrically connected to the third wiring, and

wherein the gate of the third transistor is not electrically connected to the gate of the fourth transistor.

9. The semiconductor device according to claim 8, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor have the same conductivity type.

10. The semiconductor device according to claim 8, wherein a ratio of a channel width to a channel length of the fourth transistor is higher than a ratio of a channel width to a channel length of the third transistor.

11. The semiconductor device according to claim 8,

wherein the third transistor comprises a first semiconductor layer and a first gate electrode,

wherein the fourth transistor comprises a second semiconductor layer and a second gate electrode, and

wherein an area where the second semiconductor layer and the second gate electrode overlap with each other is larger than an area where the first semiconductor layer and the first gate electrode overlap with each other.

12. The semiconductor device according to claim 8, wherein a channel formation region of at least one of the first transistor, the second transistor, the third transistor, and the fourth transistor comprises an oxide semiconductor.

13. The semiconductor device according to claim 8,

wherein the first wiring is configured to supply a first clock signal to the other of the source and the drain of the first transistor,

wherein the second wiring is configured to supply a voltage to the other of the source and the drain of the second transistor and the one of the source and the drain of the third transistor, and

wherein the third wiring is configured to supply a second clock signal to the gate of the third transistor.

14. A semiconductor device comprising:

a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; and

a first wiring, a second wiring;

a third wiring, and a fourth wiring,

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,

wherein the other of the source and the drain of the first transistor and a gate of the third transistor are electrically connected to the first wiring,

wherein a gate of the first transistor is electrically connected to one of a source and a drain of the fourth transistor,

wherein the other of the source and the drain of the second transistor and one of a source and a drain of the third transistor are electrically connected to the second wiring,

wherein a gate of the second transistor is electrically connected to a gate of the fourth transistor, one of a source and a drain of the sixth transistor, and one of a source and a drain of the seventh transistor,

wherein the other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the fourth transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the seventh transistor,

wherein the other of the source and the drain of the fifth transistor is electrically connected to the fourth wiring, and

wherein a gate of the sixth transistor is electrically connected to the third wiring.

15. The semiconductor device according to claim 14, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor have the same conductivity type.

16. The semiconductor device according to claim 14, wherein a ratio of a channel width to a channel length of the fourth transistor is higher than a ratio of a channel width to a channel length of the third transistor.

17. The semiconductor device according to claim 14,

wherein the third transistor comprises a first semiconductor layer and a first gate electrode,

wherein the fourth transistor comprises a second semiconductor layer and a second gate electrode, and

wherein an area where the second semiconductor layer and the second gate electrode overlap with each other is larger than an area where the first semiconductor layer and the first gate electrode overlap with each other.

18. The semiconductor device according to claim 14, wherein a channel foil cation region of at least one of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor comprises an oxide semiconductor.

19. The semiconductor device according to claim 14,

wherein the first wiring is configured to supply a first clock signal to the other of the source and the drain of the first transistor,

wherein the second wiring is configured to supply a voltage to the other of the source and the drain of the second transistor and the one of the source and the drain of the third transistor,

wherein the third wiring is configured to supply a second clock signal to the gate of the sixth transistor, and

wherein the fourth wiring is configured to supply a start pulse to the other of the source and the drain of the fourth transistor.