GATE STRUCTURE WITH MULTIPLE SPACERS

• US 20170243946A1
• Filed: 05/11/2017
• Published: 08/24/2017
• Est. Priority Date: 07/31/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: PAN, Chia-Ming, CHUANG, Chiang-Ming, HO, Pei-Chi, HSIEH, Ping-Pang
• Granted Patent: US 10,103,235 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND

Abstract

Semiconductor structures are provided. The semiconductor structure includes a substrate and a floating gate structure formed over the substrate. The semiconductor structure further includes a dielectric structure formed over the floating gate structure and a control gate structure formed over the dielectric structure. The semiconductor structure further includes a first spacer formed over a lower portion of a sidewall of the control gate structure and an upper spacer formed over an upper portion of the sidewall of the control gate structure. In addition, a portion of the control gate structure is in direct contact with the upper spacer.

Claims

1. A semiconductor structure, comprising:

a substrate;

a floating gate structure formed over the substrate;

a dielectric structure formed over the floating gate structure;

a control gate structure formed over the dielectric structure;

a first spacer formed over a lower portion of a sidewall of the control gate structure; and

an upper spacer formed over an upper portion of the sidewall of the control gate structure,

wherein a portion of the control gate structure is in direct contact with the upper spacer.

2. The semiconductor structure as claimed in claim 1, wherein a portion of the upper spacer overlaps with the first spacer.

3. The semiconductor structure as claimed in claim 1, further comprising:

a second spacer formed over the first spacer and over a sidewall of the floating gate structure.

4. The semiconductor structure as claimed in claim 3, further comprising:

a lower spacer formed over the second spacer and over a lower portion of the first spacer.

5. The semiconductor structure as claimed in claim 4, wherein a portion of the lower spacer is in direct contact with the floating gate structure.

6. The semiconductor structure as claimed in claim 4, further comprising:

a common source region formed adjacent to the lower spacer in the substrate; and

a contact formed over the common source region.

7. The semiconductor structure as claimed in claim 6, further comprising:

a word line structure formed at a side of the floating gate structure opposite the contact.

8. A semiconductor structure, comprising:

a floating gate structure formed over a substrate;

a dielectric structure formed over the floating gate structure;

a control gate structure formed over the dielectric structure;

a first spacer formed over a sidewall of the control gate structure;

a second spacer formed over a sidewall of the floating gate structure;

a lower spacer formed over the second spacer; and

an upper spacer formed over the first spacer and extending onto the control gate structure,

wherein the upper spacer is in direct contact with the control gate structure.

9. The semiconductor structure as claimed in claim 8, wherein the lower spacer is in direct contact with the floating gate structure.

10. The semiconductor structure as claimed in claim 8, further comprising:

a common source region formed adjacent to the lower spacer in the substrate; and

a contact formed over the common source region.

11. The semiconductor structure as claimed in claim 8, further comprising:

a cap structure formed over the control gate structure,

wherein the upper spacer further extends onto a sidewall of the cap structure.

12. The semiconductor structure as claimed in claim 8, further comprising:

a word line structure formed over the substrate,

wherein the word line structure and the lower spacer are located at opposite sides of the floating gate structure.

13. A semiconductor structure, comprising:

a substrate;

a floating gate structure formed over the substrate;

a dielectric structure formed over the floating gate structure;

a control gate structure formed over the dielectric structure;

a first spacer formed over a lower portion of a sidewall of the control gate structure; and

an upper spacer formed over an upper portion of the sidewall of the control gate structure and overlapping with the first spacer.

14. The semiconductor structure as claimed in claim 13, wherein the control gate structure is in direct contact with the upper spacer.

15. The semiconductor structure as claimed in claim 13, further comprising:

a second spacer formed over the first spacer and over a sidewall of the floating gate structure.

16. The semiconductor structure as claimed in claim 15, further comprising:

a lower spacer overlapping with both the second spacer and the first spacer.

17. The semiconductor structure as claimed in claim 16, wherein the lower spacer is in direct contact with the floating gate structure.

18. The semiconductor structure as claimed in claim 16, further comprising:

a common source region formed adjacent to the lower spacer in the substrate; and

a contact formed over the common source region.

19. The semiconductor structure as claimed in claim 18, further comprising:

a word line structure formed at a side of the floating gate structure opposite the contact.

20. The semiconductor structure as claimed in claim 18, wherein the lower spacer covers a portion of the common source region.