SYSTEMS AND METHODS FOR FABRICATING SELF-ALIGNED RESISTIVE/MAGNETIC MEMORY CELL

• US 20170244025A1
• Filed: 05/11/2017
• Published: 08/24/2017
• Est. Priority Date: 03/25/2006
• Status: Abandoned Application

• Current Assignee: 4D-S, Ltd. (4DS Memory Limited)
• Original Assignee: 4D-S, Ltd. (4DS Memory Limited)
• Inventors: Nagashima, Makoto
• Application Number:
  US15/593,216
• Publication Number:
  US 20170244025A1
• Time in Patent Office: Days
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: H10N 50/85 Magnetic active materials
• CPC Class Codes: H10N 70/011 Manufacture or treatment of multistable switching devices
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8836 Complex metal oxides, e.g. perovskites, spinels

Abstract

Systems and methods are disclosed to form a resistive random access memory (RRAM) by forming a first metal electrode layer; depositing an insulator above the metal electrode layer and etching the insulator to expose one or more metal portions; depositing a Pr_1-XCa_XMnO_S (PCMO) layer, in an electrically biased sputtering chamber, above the insulator and the metal portions, to form one or more self-aligned RRAM cells above the first metal electrode; and depositing a second metal electrode layer above the PCMO layer.

Claims

1-19. -19. (canceled)

20. A method of forming a magnetic random access memory (MRAM), the method comprising:

forming a first magnetic layer;

depositing an insulator above the magnetic layer;

etching the insulator to expose one or more magnetic layer portions;

depositing a Pr_1-xCa_xMnO₃ (PCMO) layer in an electrically biased sputtering chamber above the insulator and the magnetic layer portions, whereby one or more self-aligned MRAM cells are formed above the first magnetic layer.

21. The method of claim 20, comprising depositing and patterning an insulator layer between a wafer and the first magnetic layer.

22. The method of claim 20, wherein the electrically biased sputtering chamber comprises facing targets.

23. The method of claim 22, comprising forming via holes to connect the first magnetic layer to circuit on the wafer.

24. The method of claim 23, comprising depositing a magnetic layer above the via holes.

25. The method of claim 22, comprising depositing an adhesion layer above the first magnetic layer.

26. The method of claim 25, comprising performing chemical mechanical polishing on the vias.

27. The method of claim 20, comprising depositing a passivation film.

28. The method of claim 27, comprising performing chemical mechanical polishing on the passivated film.