GATE PRE-POSITIONING FOR FAST TURN-OFF OF SYNCHRONOUS RECTIFIER

• US 20170244333A1
• Filed: 11/22/2016
• Published: 08/24/2017
• Est. Priority Date: 02/22/2016
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: CHOI, Hangseok, HUANG, Wei-Hsuan, CHEN, Cheng-Sung
• Granted Patent: US 9,991,810 B2
• Time in Patent Office: Days
• CPC Class Codes: H02M 1/0054 Transistor switching losses periodically suspending operation of switching converter in low power mode H02M1/0035
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H02M 3/33592 having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A synchronous rectifier driver pre-positions a gate of a synchronous rectifier to allow for fast turn-off. The synchronous rectifier driver turns ON the synchronous rectifier by driving the gate at a high level for a period of time that is based on a previous conduction time of the synchronous rectifier. The synchronous rectifier driver thereafter drives the gate at a lower level that is sufficient to keep the synchronous rectifier ON. The synchronous rectifier can be quickly turned OFF by further reducing the level of the drive signal at the gate of the synchronous rectifier.

Claims

1. A synchronous rectifier driver comprising:

a first node for connecting to a drain of a synchronous rectifier, a second node for connecting to a source of the synchronous rectifier, and a third node for connecting to a gate of the synchronous rectifier; and

a gate drive circuit that is configured to increase a gate drive signal to the gate of the synchronous rectifier to a first level to turn ON the synchronous rectifier, to reduce the gate drive signal from the first level to a second level after a first time period that is based on a conduction time of the synchronous rectifier, to maintain the gate drive signal at the second level for a second time period, and to turn OFF the synchronous rectifier by reducing the gate drive signal from the second level to a third level.

2. The synchronous rectifier driver of claim 1, wherein the first time period is 50% of the conduction time of the synchronous rectifier.

3. The synchronous rectifier driver of claim 1, wherein the gate drive circuit comprises:

a first switch having a drain that is connected to the gate of the synchronous rectifier; and

a current source that generates a bias current to the gate of the synchronous rectifier to maintain the second level at the gate of the synchronous rectifier.

4. The synchronous rectifier driver of claim 3, wherein the gate drive circuit further comprises:

a second switch having a drain that is connected to the gate of the synchronous rectifier, the second switch being configured to reduce the gate drive signal from the second level to the third level to turn OFF the synchronous rectifier; and

a third switch having a source that is connected to the gate of the synchronous rectifier, the third switch being configured to increase the gate drive signal to the first level to turn ON the synchronous rectifier.

5. The synchronous rectifier driver of claim 1, wherein the synchronous rectifier driver is in an integrated circuit (IC) package and the first, second, and third nodes of the synchronous rectifier driver are pins of the IC package.

6. The synchronous rectifier driver of claim 1, wherein the synchronous rectifier is connected to a secondary winding of a transformer of a switching converter circuit.

7. The synchronous rectifier driver of claim 6, wherein the switching converter circuit is a flyback converter.

8. A method of controlling conduction of a synchronous rectifier, the method comprising:

detecting a conduction time of a synchronous rectifier in a first switching cycle;

in a second switching cycle that occurs after the first switching cycle, driving a gate of the synchronous rectifier with a gate voltage at a first level to turn ON the synchronous rectifier;

in the second switching cycle, in response to expiration of a period of time that is based on the detected conduction time of the synchronous rectifier in the first switching cycle, reducing the gate voltage to a second level that is lower than the first level, wherein the second level keeps the synchronous rectifier ON; and

in the second switching cycle, turning OFF the synchronous rectifier by further reducing the gate voltage from the second level.

9. The method of claim 8, wherein the period of time is adaptively set to be 50% of the detected conduction time of the synchronous rectifier in the first switching cycle.

10. The method of claim 8, wherein detecting the conduction time of the synchronous rectifier in the first switching cycle comprises:

in the first switching cycle, charging a first capacitor during the conduction time of the synchronous rectifier in the first switching cycle; and

in the first switching cycle, storing in a second capacitor a peak of a charge of the first capacitor.

11. The method of claim 10, further comprising:

in the second switching cycle, setting the period of time to be based on a percentage of a charge stored in the second capacitor.

12. A switching converter circuit comprising:

a primary-side switch on a primary side of a transformer;

a synchronous rectifier on a secondary side of the transformer; and

a synchronous rectifier driver on the secondary side of the transformer, the synchronous rectifier driver comprising a first node connected to a drain of the synchronous rectifier, a second node connected to a gate of the synchronous rectifier, a third node connected to a source of the synchronous rectifier, and a pre-positioning gate driver that generates a gate drive signal to the gate of the synchronous rectifier, sets the gate drive signal to a first level to turn ON the synchronous rectifier, reduces the gate drive signal from the first level to a second level that keeps the synchronous rectifier ON, and reduces the gate drive signal from the second level to turn OFF the synchronous rectifier.

13. The switching converter circuit of claim 12, wherein the pre-positioning gate driver reduces the gate drive signal from the first level to the second level in response to expiration of a time period that is based on a conduction time of the synchronous rectifier.

14. The switching converter circuit of claim 13, wherein the time period is equal to 50 percent of the conduction time of the synchronous rectifier.

15. The switching converter circuit of claim 12, wherein the first, second, and third nodes of the synchronous rectifier driver are pins of an integrated circuit (IC) package of the synchronous rectifier driver.

16. The switching converter circuit of claim 12, wherein the pre-positioning gate driver comprises:

a first switch having a drain that is connected to the gate of the synchronous rectifier; and

a current source that generates a bias current to the gate of the synchronous rectifier to maintain the second level at the gate of the synchronous rectifier.

17. The switching converter circuit of claim 16, wherein the pre-positioning gate driver further comprises:

a second switch having a drain that is connected to the gate of the synchronous rectifier, the second switch being configured to reduce the gate drive signal from the second level to turn OFF the synchronous rectifier; and

a third switch having a source that is connected to the gate of the synchronous rectifier, the third switch being configured to increase the gate drive signal to the first level to turn ON the synchronous rectifier.

18. The switching converter circuit of claim 12, wherein the switching converter circuit comprises a flyback converter.

19. The switching converter circuit of claim 12, wherein the synchronous rectifier driver further comprises:

a first capacitor that is charged during a conduction time of the synchronous rectifier in a first switching cycle; and

a second capacitor that stores a peak of a charge in the first capacitor in the first switching cycle.

20. The switching converter circuit of claim 19, wherein the gate drive signal is reduced from the first level to the second level in a second switching cycle that follows the first switching cycle after a time period that is based on a charge stored in the second capacitor.