An Electronic Latch Circuit and a Generic Multi-Phase Signal Generator

• US 20170244393A1
• Filed: 05/04/2015
• Published: 08/24/2017
• Est. Priority Date: 12/02/2014
• Status: Active Grant

• Current Assignee: Telefonaktiebolaget LM Ericsson
• Original Assignee: Telefonaktiebolaget LM Ericsson
• Inventors: Bagger, Reza
• Granted Patent: US 10,250,237 B2
• Time in Patent Office: Days
• CPC Class Codes: H03K 19/20 characterised by logic function, e.g. AND, OR, NOR, NOT circuits H03K19/003 - H03K19/01 take precedence
• CPC Class Codes: H03K 21/10 comprising logic circuits
• CPC Class Codes: H03K 23/425 using bistables
• CPC Class Codes: H03K 23/483 with a base which is an odd number
• CPC Class Codes: H03K 3/356 Bistable circuits
• CPC Class Codes: H03K 3/356104 using complementary field-effect transistors H03K3/35625 takes precedence
• CPC Class Codes: H03K 3/356139 with synchronous operation
• CPC Class Codes: H03K 3/35625 using complementary field-effect transistors
• CPC Class Codes: H03K 3/37 by the use, as active elements, of gas-filled tubes, e.g. astable trigger circuits H03K3/55 takes precedence
• CPC Class Codes: H03K 5/15066 using bistable devices H03K5/15093 takes precedence
• CPC Class Codes: H04B 1/40 Circuits

Abstract

An electronic latch circuit (100) and a multi-phase signal generator (300) are disclosed. The electronic latch circuit (100) comprises an output circuit (105) comprising a first output (X, 106), a second output (Y, 107) and a third output (Z, 108). The electronic latch circuit (100) further comprises an input circuit (101) comprising a first input (A, 102), a second input (B, 103) and a clock signal input (CLK, 104). The electronic latch circuit (100) is configured to change state based on input signals at the inputs (A, B, CLK) of the input circuit (101) and a present state of the output circuit (105). The multi-phase signal generator (300) comprises a plurality N of the electronic latch circuit (100) for generating N phase signals with individual phases. The plurality N of the electronic latch circuit (100) are cascaded with each other.

Claims

1-7. -7. (canceled)

8. An electronic latch circuit, comprising:

an output circuit comprising a first output, a second output, and a third output;

an input circuit comprising a first input, a second input, and a clock signal input;

wherein the input circuit comprises;

a first Metal Oxide Semiconductor (MOS) transistor with a gate connected to the first input, a source connected to a first voltage potential, and a drain connected to a first node of the output circuit;

a second MOS transistor with a gate connected to the second input, a source connected to the first voltage potential, and a drain connected to a second node of the output circuit; and

a third MOS transistor with a gate connected to the clock signal input, a source connected to a second voltage potential, and a drain connected to a third node of the output circuit;

wherein the output circuit comprises;

a fourth MOS transistor with a drain connected to the first node, a gate connected to the second node, and a source connected to the third node; and

a fifth MOS transistor with a drain connected to the second node, a gate connected to the first node, and a source connected to the third node;

wherein the first output is connected to the first node, the second output is connected to the second node, and the third output is connected to the third node;

wherein the electronic latch circuit is configured to change state based on input signals at the inputs of the input circuit and a present state of the output circuit.

9. A multi-phase signal generator for generating N phase signals with individual phases, wherein the multi-phase signal generator comprises:

a first overall clock signal input, a second overall clock signal input, and N overall outputs;

a plurality (N) of electronic latch circuits cascaded with each other;

wherein each of the electronic latch circuits comprises;

an output circuit comprising a first output, a second output, and a third output;

an input circuit comprising a first input, a second input, and a clock signal input;

wherein the input circuit comprises;

a first Metal Oxide Semiconductor (MOS) transistor with a gate connected to the first input, a source connected to a first voltage potential, and a drain connected to a first node of the output circuit;

a second MOS transistor with a gate connected to the second input, a source connected to the first voltage potential, and a drain connected to a second node of the output circuit; and

a third MOS transistor with a gate connected to the clock signal input, a source connected to a second voltage potential, and a drain connected to a third node of the output circuit;

wherein the output circuit comprises;

a fourth MOS transistor with a drain connected to the first node, a gate connected to the second node, and a source connected to the third node; and

a fifth MOS transistor with a drain connected to the second node, a gate connected to the first node, and a source connected to the third node;

wherein the first output is connected to the first node, the second output is connected to the second node, and the third output is connected to the third node;

wherein the electronic latch circuit is configured to change state based on input signals at the inputs of the input circuit and a present state of the output circuit;

wherein the first and second outputs of the i-th electronic latch circuit are coupled to the first and second inputs of the (i+1)-th electronic latch circuit, wherein i=1, 2, . . . N−

1; and

wherein the first and second outputs of the N-th electronic latch circuit are cross coupled to the first and second inputs of the first electronic latch circuit to form a negative feedback;

wherein the first overall clock input is connected to the clock signal inputs of the k-th electronic latch circuits, wherein k is an odd number, and k=1, 3, . . . N−

1;

wherein the second overall clock input is connected to the clock signal inputs of the j-th electronic latch circuits, wherein j is an even number, and j=2, 4, . . . N; and

wherein the N phase signals are generated via the outputs of each electronic latch circuit.

10. The multi-phase signal generator of claim 9:

wherein the multi-phase signal generator is configured to receive a first clock signal at the first overall clock signal input, and receive a second clock signal at the second overall clock signal input;

wherein the second clock signal is the inverse of the first clock signal; and

wherein the N phase signals are generated at the third outputs of each electronic latch circuit.

11. The multi-phase signal generator of claim 9:

wherein the multi-phase signal generator is configured to receive a first clock signal at the first overall clock signal input, and receive a second clock signal at the second overall clock signal input;

wherein the second clock signal is the inverse of the first clock signal; and

wherein the multi-phase signal generator further comprises N AND-gating circuits, and the N phase signals are generated by AND-gating signals generated at the first and second outputs of each electronic latch circuit.

12. The multi-phase signal generator of claim 9, wherein N is an even number.

13. An electronic device, comprising:

a multi-phase signal generator for generating N phase signals with individual phases;

wherein the multi-phase signal generator comprises;

a first clock overall signal input, a second overall clock signal input, and N outputs;

a plurality (N) of electronic latch circuits cascaded with each other;

wherein each of the electronic latch circuits comprises;

an output circuit comprising a first output, a second output, and a third output;

an input circuit comprising a first input, a second input, and a clock signal input;

wherein the input circuit comprises;

a first Metal Oxide Semiconductor (MOS) transistor with a gate connected to the first input, a source connected to a first voltage potential, and a drain connected to a first node of the output circuit;

a second MOS transistor with a gate connected to the second input, a source connected to the first voltage potential, and a drain connected to a second node of the output circuit; and

a third MOS transistor with a gate connected to the clock signal input, a source connected to a second voltage potential, and a drain connected to a third node of the output circuit;

wherein the output circuit comprises;

a fourth MOS transistor with a drain connected to the first node, a gate connected to the second node, and a source connected to the third node; and

a fifth MOS transistor with a drain connected to the second node, a gate connected to the first node, and a source connected to the third node;

wherein the first output is connected to the first node, the second output is connected to the second node, and the third output is connected to the third node;

wherein the electronic latch circuit is configured to change state based on input signals at the inputs of the input circuit and a present state of the output circuit;

wherein the first and second outputs of the i-th electronic latch circuit are coupled to the first and second inputs of the (i+1)-th electronic latch circuit, wherein i=1, 2, . . . N−

1; and

wherein the first and second outputs of the N-th electronic latch circuit are cross coupled to the first and second inputs of the first electronic latch circuit to form a negative feedback;

wherein the first overall clock input is connected to the clock signal inputs of the k-th electronic latch circuits, wherein k is an odd number, and k=1, 3, . . . N−

1;

wherein the second overall clock input is connected to the clock signal inputs of the j-th electronic latch circuits, wherein j is an even number, and j=2, 4, . . . N; and

wherein the N phase signals are generated via the outputs of each electronic latch circuit.

14. The electronic device of claim 13, wherein the electronic device is a transceiver.