SYNCHRONOUS TRANSFER OF STREAMING DATA IN A DISTRIBUTED ANTENNA SYSTEM

• US 20170244541A1
• Filed: 05/08/2017
• Published: 08/24/2017
• Est. Priority Date: 03/31/2010
• Status: Active Grant

• Current Assignee: Outdoor Wireless Networks LLC (CommScope Holding Company, Inc.)
• Original Assignee: CommScope Technologies, LLC (CommScope Holding Company, Inc.)
• Inventors: McAllister, Donald R., Ranson, Christopher Goodman, Phillips, Fred William
• Granted Patent: US 10,027,469 B2
• Time in Patent Office: Days
• CPC Class Codes: H04J 3/0658 Clock or time synchronisation among packet nodes
• CPC Class Codes: H04L 1/0625 Transmitter arrangements
• CPC Class Codes: H04L 1/0631 Receiver arrangements
• CPC Class Codes: H04L 7/0087 Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04W 88/085 Access point devices with remote components

Abstract

Method and apparatus for generating a jitter reduced clock signal from signal transmitted over a communication medium includes receiving, with high speed data interface circuitry, a modulated signal that includes a binary encoded data stream. A recovered clock signal is generated from the modulated signal and tracks the long-term drift in the modulated signal. A jitter reduced clock signal is generated by filtering the recovered clock signal with a filtering circuit having a bandwidth sufficient to remove jitter while allowing the jitter reduced clock signal to track the drift in the modulated signal.

Claims

1. A communication system, comprising:

a first unit configured to clock an encoded data stream onto a data interface using a modulated signal; and

at least one second unit configured to receive the modulated signal and encoded data stream from the first unit, the at least one second unit including;

a circuit configured to generate a jitter reduced clock signal by removing jitter from a recovered clock signal while allowing the jitter reduced clock signal to track long-term drift in the modulated signal, wherein the at least one second unit is configured to generate the recovered clock signal from the modulated signal.

2. The system of claim 1, wherein the circuit includes at least one of a phase-locked loop, a frequency-locked loop, or a narrowband filter.

3. The system of claim 1, further comprising a scaling circuit configured to scale a frequency of the recovered clock signal to generate an output signal at a predetermined target frequency.

4. The system of claim 1, wherein the data interface is coupled to a communication medium, between the first unit and the at least one second unit, having at least one twisted pair cable.

5. The system of claim 1, the first unit further including:

RF transceiver circuitry configured to communicate with a base transceiver station;

an auxiliary interface configured to communicate at least one of control data, maintenance data, Ethernet data, or WiFi data; and

a processor configured to multiplex data from the RF transceiver circuitry and the auxiliary interface for transmission to the at least one second unit via the data interface, the processor further configured to de-multiplex data received from the data interface for transmission to the base transceiver station via the RF transceiver circuitry.

6. The system of claim 1, wherein the data interface circuitry includes at least a one gigabit per second (Gbps) Ethernet interface.

7. The system of claim 6, wherein the Ethernet interface is synchronous or asynchronous.

8. A unit for use in a communication system comprising:

a data interface configured to couple the unit to an other unit of the communication system and to transceive a modulated signal with the other unit; and

a circuit configured to generate a jitter reduced clock signal by removing jitter from a recovered clock signal while allowing the jitter reduced clock signal to track long-term drift in the modulated signal, wherein the unit is configured to generate a recovered clock signal from the modulated signal.

9. The unit of claim 8, wherein the circuit includes at least one of a phase-locked loop, a frequency-locked loop, or a narrowband filter.

10. The unit of claim 8, further comprising a scaling circuit configured to scale a frequency of the recovered clock signal to generate an output signal at a predetermined target frequency.

11. The unit of claim 8, further comprising:

RF transceiver circuitry configured to communicate cellular and non-cellular data with a subscriber unit;

an auxiliary interface configured to communicate at least one of control data, maintenance data, Ethernet data, or WiFi data; and

a processing unit configured to de-multiplex data from the data interface for transmission by the RF transceiver circuitry or the auxiliary interface, the processing unit is further configured to multiplex data from the RF transceiver circuitry and the auxiliary interface for transmission on the data interface.

12. The unit of claim 8, wherein the processing unit is configured to adjust the rate of data being transmitted on the data interface to match the capability of that data interface by excluding low priority data from the multiplexed stream.

13. The unit of claim 8, wherein data communicated to the unit via the data interface includes at least one of digitized RF cellular voice data, digitized RF non-cellular voice data, digitized RF cellular data, digitized RF non-cellular data, control data, maintenance data, Ethernet data, or WiFi data.

14. The unit of claim 8, wherein the data interface includes at least a one gigabit per second (Gbps) Ethernet interface.

15. The unit of claim 14, wherein the Ethernet interface is synchronous or asynchronous.

16. A method comprising:

receiving a modulated signal including an encoded data stream; and

generating a jitter reduced clock signal by removing jitter from a recovered clock signal while allowing the jitter reduced clock signal to track long-term drift in the modulated signal, wherein the recovered clock signal is generated from the modulated signal.

17. The method of claim 16, further comprising generating the jitter reduced clock signal by filtering the recovered clock signal using at least one of a phase-locked loop, a frequency-locked loop, or a narrowband filter.

18. The method of claim 16, further comprising scaling a frequency of the jitter reduced clock signal to produce at least one scaled clock signal.

19. The method of claim 16, wherein receiving the modulated signal that includes the encoded data stream comprises receiving the modulated signal using at least a one gigabit per second (Gbps) Ethernet interface.

20. The method of claim 16, wherein the communication medium is a communication cable having at least one twisted pair cable.