TESTING HOLDERS FOR CHIP UNIT AND DIE PACKAGE

• US 20170248652A1
• Filed: 05/12/2017
• Published: 08/31/2017
• Est. Priority Date: 03/14/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: WANG, Mill-Jer, LIU, Kuo-Chuan, PENG, Ching-Nen, LIN, Hung-Chih, CHEN, Hao
• Granted Patent: US 10,067,181 B2
• Time in Patent Office: Days
• CPC Class Codes: G01R 1/0483 Sockets for un-leaded IC's having matrix type contact fields, e.g. BGA or PGA devices; Sockets for unpackaged, naked chips for IC's with connecting points around the edges only G01R1/0433
• CPC Class Codes: G01R 1/06722 Spring-loaded
• CPC Class Codes: G01R 31/2867 Handlers or transport devices, e.g. loaders, carriers, trays
• CPC Class Codes: G01R 31/2875 related to heating
• CPC Class Codes: G01R 31/2893 Handling, conveying or loading, e.g. belts, boats, vacuum fingers G01R31/2867 takes precedence; handling semiconductor devices or wafers during manufacture or treatment H01L21/67
• CPC Class Codes: G01R 31/318513 Test of Multi-Chip-Moduls

Abstract

A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body.

Claims

1. A testing holder for a chip unit, comprising:

a holder body configured to contain the chip unit; and

a pressure releasing device formed on the holder body configured to release an insertion pressure when the chip unit is inserted in the holder body.

2. The testing holder of claim 1, wherein the holder body further comprises a surrounding wall, and the surrounding wall defines an inner space configured for containing and testing the chip unit.

3. The testing holder of claim 2, wherein the surrounding wall further has a tilted surface configured to guide therein an insertion of the chip unit and to avoid an edge scratch on the chip unit.

4. The testing holder of claim 2, wherein the surrounding wall has an upper surrounding wall including a first and a second openings with a first size and a lower surrounding wall including a third opening with a second size, the upper surrounding wall and the lower surrounding wall are connected by plural guide pins, and is configured so that the chip unit is insertable into the holder body via the first, the second, and the third openings, and the first size is equal to a size of the chip unit to fix an inserted chip unit.

5. The testing holder of claim 2, wherein the testing holder has an outer dimension kept unchanged and an inner dimension adapted to a size of a chip unit to be inserted in the testing holder.

6. A multi site holding frame for a plurality of chip units, comprising:

a first holder frame having a plurality of testing holders, each of the plurality of testing holders including a holder body configured to contain one of the plural chip units,

wherein the holder frame comprises;

a power supply, and a temperature controller; and

a multi site probe card,

wherein the multi site probe card includes plural contact probes and plural contactless coils.

7. The multi site holding frame of claim 6, further comprising a second holder frame, plural frame guiding pins and a multi site probe card having plural probing devices to probe one of a contact and a contactless transmission, wherein the holder body has an upper surrounding wall including a first and a second openings and a lower surrounding wall including a third opening, the upper surrounding wall and the lower surrounding wall are connected by plural guide pins, and the one of the chip units is insertable into the holder body via the first, the second, and the third openings.

8. The multi site holding frame of claim 7, wherein each of the second holder frame and the first holder frame has plural guiding pin holes, the second holder frame is used to contain all of the upper surrounding walls, the first holder frame is used to contain all of the lower surrounding walls, and the second holder frame and the first holder frame are connected by the plural frame guiding pins inserted into the plural guiding pin holes.

9. The multi site holding frame of claim 6, wherein the holder body has a surrounding wall, and the surrounding wall is disposed on a bottom plate of the holder body and defines an inner space for containing and testing the one of the chip units.

10. The multi site holding frame of claim 6, wherein each of the plurality of testing holders is replaceable.

11. The multi site holding frame of claim 6, wherein the first holder frame further comprises an alignment mark for frame positioning, and the first holder frame is reusable.

12. The multi site holding frame of claim 6, wherein each of the plurality of testing holders have a same outer dimension.

13. The multi site holding frame of claim 12, wherein inner dimensions of each of the plurality of testing holders are adapted to a size of the chip unit being tested.

14. A method of testing a plurality of chip units, comprising:

inserting a first chip unit into a testing holder and inserting a second chip unit into a second testing holder,

wherein the first chip unit and the second chip unit have different dimensions, and the first testing holder and second testing holder have same outer dimensions;

inserting the first testing holder and the second testing holder into a first open recess and a second open recess, respectively, of a holder frame;

positioning a multi-site probe card having a plurality of probe contacts and a plurality of contactless coils over the holder frame; and

testing the first chip unit and the second chip unit to determine whether the first and second chip units are defective chip units.

15. The method of claim 14, wherein each of the chip units has a test contactor, and the test contactor is one selected from a group consisting of a bump, a pad, a contactless coil, a hybrid contactless, and a combination thereof, and the chip units are tested through the test contactor.

16. The method of claim 14, wherein the chip units are subject to a PoP testing, a CoWoS/CoCoS pre-bond testing, or a CoCoS post-bond testing.

17. The method of claim 14, further comprising dicing the chip units after testing.

18. The method of claim 14, wherein the first testing holder and the second testing holder further comprise a surrounding wall, and the surrounding wall has a tilted surface configured to guide therein an insertion of the first and second chip units to avoid an edge scratch on the chip units.

19. The method of claim 18, wherein the surrounding wall has an upper surrounding wall including a first and a second openings with a first size and a lower surrounding wall including a third opening with a second size, the upper surrounding wall and the lower surrounding wall are connected by plural guide pins, and is configured so that the chip units are insertable into the testing holder via the first, the second, and the third openings, and the first size is equal to a size of the chip unit to fix an inserted chip unit.

20. The method of claim 14, further comprising using a temperature controller to control the temperature of the testing within a range of from about −

50°

C. to about 150°

C.