BANDWIDTH REDUCTION FOR INSTRUCTION TRACING

• US 20170249146A1
• Filed: 02/29/2016
• Published: 08/31/2017
• Est. Priority Date: 02/29/2016
• Status: Abandoned Application

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: VENKUMAHANTI, Suresh Kumar, MORA, Venkatarami
• Application Number:
  US15/057,111
• Publication Number:
  US 20170249146A1
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/36 Preventing errors by testing or debugging software
• CPC Class Codes: G06F 11/3636 by tracing the execution of the program

Abstract

Systems and methods pertain to reducing bandwidth of instruction tracing for a processor, using an Embedded Trace Macrocell (ETM). Packets, which include trace information for load/store instructions executed in the processor, are generated. A P-Header comprising commit information for load/store instructions of up to a maximum number of two or more packets is generated. The P-Header is generated for the maximum number of two or more packets if none of the load/store instructions in the maximum number of two or more packets were killed. If a load/store instruction in a packet was killed, a P-Header comprising commit information for the packet comprising the load/store instruction which was killed is generated and placed in an instruction trace immediately after that packet, even if the maximum number is not reached.

Claims

1. A method of instruction tracing, the method comprising:

generating packets comprising trace information for load/store instructions executed in a processor; and

generating a P-Header comprising commit information for load/store instructions of a maximum number of two or more packets, if none of the load/store instructions in the maximum number of two or more packets were killed.

2. The method of claim 1, further comprising placing the P-Header packet immediately after a sequence of the maximum number of two or more packets in an instruction trace, if none of the load/store instructions in the maximum number of two or more packets were killed.

3. The method of claim 2, further comprising providing the instruction trace to an external trace analyzer or decompressor for reconstructing an instruction execution sequence.

4. The method of claim 1, comprising receiving a kill indication that a load/store instruction in a first packet was killed and generating a P-Header immediately following the first packet.

5. The method of claim 4, further comprising placing the P-Header immediately after the first packet in an instruction trace.

6. The method of claim 1, wherein the maximum number is 18.

7. The method of claim 1, wherein the packets comprise at least one of an E-type packet or an N-type packet, wherein an E-type packet comprises a branch instruction which was taken and an N-type packet comprises a branch instruction which was not-taken.

8. The method of claim 1, wherein the instruction tracing is performed in an Embedded Trace Macrocell (ETM).

9. An apparatus comprising:

a packet generator configured to generate packets comprising trace information for load/store instructions executed in a processor; and

a P-Header generator configured to generate a P-Header comprising commit information for load/store instructions of a maximum number of two or more packets, if none of the load/store instructions in the maximum number of two or more packets were killed.

10. The apparatus of claim 9, wherein the P-Header generator is configured to place the P-Header packet immediately after a sequence of the maximum number of two or more packets in an instruction trace, if none of the load/store instructions in the maximum number of two or more packets were killed.

11. The apparatus of claim 9, further comprising an external trace analyzer or decompressor configured to receive the instruction trace and reconstruct an instruction execution sequence.

12. The apparatus of claim 9, wherein the P-Header generator is configured to receive a kill indication that a load/store instruction in a first packet was killed and generate a P-Header immediately after the first packet.

13. The apparatus of claim 12, wherein the P-Header generator is configured to place the P-Header immediately after the first packet in an instruction trace.

14. The apparatus of claim 9, wherein the maximum number is 18.

15. The apparatus of claim 9, wherein the packets comprise at least one of an E-type packet or an N-type packet, wherein an E-type packet comprises a branch instruction which was taken and an N-type packet comprises a branch instruction which was not-taken.

16. The apparatus of claim 9, comprising an Embedded Trace Macrocell (ETM) configured to trace the instructions.

17. The apparatus of claim 9, integrated into a device, selected from the group consisting of a set top box, a music player, a video player, an entertainment unit, a navigation device, a personal digital assistant (PDA), a fixed location data unit, a computer, a laptop, a tablet, a communications device, and a mobile phone.

18. An apparatus comprising:

means for generating packets comprising trace information for load/store instructions executed in a processor; and

means for generating a P-Header comprising commit information for load/store instructions of a maximum number of two or more packets if none of the load/store instructions in the maximum number of two or more packets were killed.

19. The apparatus of claim 18, further comprising means for placing the P-Header packet immediately after a sequence of the maximum number of two or more packets in an instruction trace if none of the load/store instructions in the maximum number of two or more packets were killed.

20. The apparatus of claim 18, further comprising means for receiving the instruction trace and reconstructing an instruction execution sequence.

21. The apparatus of claim 18, further comprising means for receiving a kill indication that a load/store instruction in a first packet was killed and means for generating a P-Header immediately after the first packet.

22. The apparatus of claim 21, further comprising means for placing the P-Header immediately after the first packet in an instruction trace.