METHODS AND APPARATUS FOR LOADING FIRMWARE ON DEMAND

• US 20170249163A1
• Filed: 09/22/2016
• Published: 08/31/2017
• Est. Priority Date: 02/29/2016
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Petkov, Vladislav, Zhang, Haining, Sanghi, Karan, Garg, Saurabh
• Granted Patent: US 10,558,580 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 12/1441 for a range
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 2212/1008 Correctness of operation, e.g. memory ordering
• CPC Class Codes: G06F 2212/1052 Security improvement
• CPC Class Codes: G06F 2212/1056 Simplification
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: G06F 2213/0026 PCI express
• CPC Class Codes: G06F 3/0626 Reducing size or complexity of storage systems
• CPC Class Codes: G06F 3/0637 Permissions
• CPC Class Codes: G06F 3/0665 at area level, e.g. provisioning of virtual or logical volumes
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: G06F 8/63 Image based installation; Cloning; Build to order

Abstract

Methods and apparatus for enabling a peripheral processor to retrieve and load firmware for execution within the constraints of its memory. The peripheral processor is allocated a portion of the host processor'"'"'s memory, to function as a logical secondary and tertiary memory for memory cache operation. The described embodiments enable the peripheral processor to support much larger and more complex firmware. Additionally, a multi-facetted locking mechanism is described which enables the peripheral processor and the host processor to access the secondary memory, while minimally impacting the other processor.

Claims

1. A method for initializing firmware for execution on a processor with limited access to memory, comprising:

resetting a peripheral processor;

establishing a physical link interface;

initializing a secondary storage;

loading the peripheral processor with an initial image; and

causing the peripheral processor to execute the initial image.

2. The method of claim 1, wherein the resetting of the peripheral processor comprises holding the peripheral processor in a reset condition until after the loading of the peripheral processor with the initial image.

3. The method of claim 2, further comprising halting the peripheral processor from executing one or more instructions at least until the loading of the peripheral processor with the initial image.

4. The method of claim 1, wherein the establishing of the physical link interface comprises establishing the physical link interface as part of the peripheral processor'"'"'s boot process.

5. The method of claim 4, wherein the establishing of the physical link interface comprises configuring one or more channel interface drivers.

6. The method of claim 1, wherein the initializing of the secondary storage comprises fetching a firmware image from a tertiary storage and storing the firmware image in the secondary storage.

7. The method of claim 1, wherein the causing of the peripheral processor to execute the initial image comprises causing the peripheral processor to execute a first firmware host driver and causing the peripheral processor to execute a primary firmware image.

8. An electronic device configured to initialize firmware for execution on a processor with limited access to memory, comprising:

a host processor;

a peripheral processor;

a physical bus interface configured to couple the host processor to the peripheral processor; and

a software framework configured to be executed by the host processor and the peripheral processor, the software framework comprising logic configured to;

reset the peripheral processor through use of the host processor;

establish a communication link between the peripheral processor and the host processor using the physical bus interface;

initialize a secondary storage;

load the peripheral processor with an initial image; and

cause the peripheral processor to execute the initial image.

9. The electronic device of claim 8, wherein the host processor is configured to load into an execution memory associated with the peripheral processor the initial image while the peripheral processor is concurrently held in a reset condition.

10. The electronic device of claim 9, wherein the establishment of the communication link is initialized at least in part based upon a main firmware image associated with the electronic device.

11. The electronic device of claim 10, wherein the establishment of the communication link is performed as part of the peripheral processor'"'"'s boot process.

12. The electronic device of claim 10, wherein the establishment of the communication link is performed as part of the host processor'"'"'s boot sequence.

13. The electronic device of claim 8, wherein the initialization of the secondary storage comprises an initialization of an area of shared memory for the secondary storage by the host processor, the area of shared memory comprising at least a portion of the peripheral processor'"'"'s firmware image.

14. A peripheral processing device, comprising:

a processing unit;

a physical bus interface in communication with the processing unit, the physical bus interface coupled to a communications link;

an array of registers that is coupled to the communications link; and

a memory structure that is coupled to the communications link;

wherein the peripheral processing device is further configured to;

receive a reset signal from a host processor via the communications link;

receive a portion of a firmware image from the host processor while the peripheral processing device is held in a reset condition; and

execute the portion of the firmware image.

15. The peripheral processing device of claim 14, wherein the peripheral processing device is further configured to:

generate an exception when the peripheral processing device attempts to access a location in a page that is not held within the memory structure of the peripheral processing device.

16. The peripheral processing device of claim 15, wherein the peripheral processing device is further configured to:

upon generation of the exception, notify a firmware peripheral driver of the exception; and

receive the page from a secondary storage device.

17. The peripheral processing device of claim 14, wherein the peripheral processing device is further configured to receive one or more loadable on-demand firmware modules.

18. The peripheral processing device of claim 17, wherein the portion of the firmware image comprises a first firmware host driver and a primary firmware image.

19. The peripheral processing device of claim 18, wherein upon receipt of the first firmware host driver and the primary firmware image, the peripheral processing device is configured to be released from the reset condition.

20. The peripheral processing device of claim 18, wherein the peripheral processing device is further configured to:

utilize the first firmware host driver to issue a request for at least one of the one or more loadable on-demand firmware modules.