DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME

• US 20170250203A1
• Filed: 05/12/2017
• Published: 08/31/2017
• Est. Priority Date: 08/12/2013
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: KIM, JI-SUN, KIM, JI-HYUN, CHOI, SHIN-IL, KWON, YEONG-KEUN
• Granted Patent: US 10,446,587 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1244 for preventing breakage, peeling or short circuiting
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods

Abstract

A display substrate includes a switching element disposed in a display region that is electrically connected to a gate line, a data line, and a first electrode in a peripheral region adjacent to the display region that includes a first conductive pattern formed from a first conductive layer that includes a same material as the gate line, a first line connecting part disposed in the peripheral region that includes the first conductive pattern, a second conductive pattern that overlaps the first conductive pattern and formed, an organic layer that partially exposes the second conductive pattern, and a third conductive pattern electrically connected to the second conductive pattern that contacts the partially exposed second conductive pattern, and a fourth conductive pattern that electrically connects the first conductive pattern of the pad part and the third conductive pattern of the first line connecting part.

Claims

1. A display substrate comprising:

a switching element disposed in a display region that connects with a gate line, a data line and a first electrode; and

a pad part disposed in a peripheral region adjacent to the display region that includes a first conductive pattern formed from a first conductive layer that includes a same material as the gate line, and a second conductive pattern that contacts the first conductive pattern.

2. The display substrate of claim 1, wherein the switching element comprises:

a source electrode and a drain electrode formed from the first conductive layer; and

a gate electrode formed from a third conductive layer.

3. The display substrate of claim 1, wherein the second conductive pattern is formed from a same layer as the first electrode.

4. The display substrate of claim 1, wherein the second conductive pattern includes a transparent conductive material.

5. The display substrate of claim 1, wherein the pad part further comprises:

a third conductive pattern disposed on the second conductive pattern that electrically connects to the second conductive pattern.

6. The display substrate of claim 5, further comprising a second electrode disposed on the first electrode that overlaps the first electrode, wherein the third conductive pattern is formed from a same layer as the second electrode.

7. The display substrate of claim 5, wherein the third conductive pattern includes a transparent conductive material.

8. A method of manufacturing a display substrate comprising:

forming a first conductive pattern on a base substrate;

forming a second conductive pattern on the first conductive pattern, wherein the second conductive pattern is formed from a same layer as a source electrode and a drain electrode;

forming an organic layer on the second conductive pattern; and

partially removing the organic layer to expose a portion of the second conductive pattern.

9. The method of claim 8, further comprising forming a third conductive pattern on the second conductive pattern to cover the portion of the second conductive pattern exposed by the organic layer.

10. The method of claim 9, wherein the third conductive pattern is formed from a same layer as a first electrode electrically connected to the drain electrode.

11. The method of claim 9, further comprising:

forming a protective layer on the third conductive pattern;

patterning the protective layer to expose a portion of the first conductive pattern and a portion of the third conductive pattern; and

forming a fourth conductive pattern on the partially exposed first conductive pattern and the third conductive pattern.

12. The method of claim 8, wherein the first conductive pattern is formed from a same layer as a gate electrode.

13. The method of claim 11, wherein the third conductive pattern is formed from a same layer as a first electrode electrically connected to the drain electrode, and the fourth conductive pattern is formed from a same layer as a second electrode supplied with a common voltage.