SILICON CARBIDE SEMICONDUCTOR DEVICE
First Claim
Patent Images
1. A silicon carbide semiconductor device, comprising:
- an n-type heavily doped substrate;
an n-type drift layer disposed on the substrate, having a first doping concentration;
a plurality of doped regions disposed and spaced apart in the n-type drift layer, wherein a first junction field-effect region is formed between the doped regions, and each of the doped region comprises a p-type well, an n-type heavily doped region disposed in the p-type well, a plurality of p-type heavily doped regions abutting the n-type heavily doped region and overlapping with a portion of the p-type well, and at least one second junction field-effect region enclosed by the p-type well;
a gate dielectric disposed on the n-type drift layer;
a gate electrode disposed on the gate dielectric;
an interlayer dielectric disposed on the gate dielectric and the gate electrode;
a plurality of source openings passing through the interlayer dielectric and the gate dielectric until a portion of the n-type heavily doped region and a portion of the p-heavily doped region are reached;
a plurality of junction openings passing through the interlayer dielectric and the gate dielectric until the second junction field-effect region, a portion of the p-type well and a portion of the p-type heavily doped region are reached;
a plurality of gate openings passing through the interlayer dielectric to the gate electrode;
a first metal layer disposed at the bottom side of the source opening to form an ohmic contact with a portion of the n-type heavily doped region and a portion of the p-type heavily doped region; and
a second metal layer comprising a first portion and a second portion, wherein the first portion covers the source openings and is electrically connected to the first metal layer;
the first portion covers the junction openings to faun a Schottky contact with the second junction field-effect region; and
the second portion covers the gate openings and is electrically insulated from the first portion.
2 Assignments
0 Petitions
Accused Products
Abstract
The present invention is related to a silicon carbide semiconductor device which employs a silicon carbide substrate to form an integrated device. The integrated device of the present invention comprises a metal oxide semiconductor field-effect transistor (MOSFET) and an integrated junction barrier Schottky (JBS) diode in an anti-parallel connection with the MOSFET.
12 Citations
11 Claims
-
1. A silicon carbide semiconductor device, comprising:
-
an n-type heavily doped substrate; an n-type drift layer disposed on the substrate, having a first doping concentration; a plurality of doped regions disposed and spaced apart in the n-type drift layer, wherein a first junction field-effect region is formed between the doped regions, and each of the doped region comprises a p-type well, an n-type heavily doped region disposed in the p-type well, a plurality of p-type heavily doped regions abutting the n-type heavily doped region and overlapping with a portion of the p-type well, and at least one second junction field-effect region enclosed by the p-type well; a gate dielectric disposed on the n-type drift layer; a gate electrode disposed on the gate dielectric; an interlayer dielectric disposed on the gate dielectric and the gate electrode; a plurality of source openings passing through the interlayer dielectric and the gate dielectric until a portion of the n-type heavily doped region and a portion of the p-heavily doped region are reached; a plurality of junction openings passing through the interlayer dielectric and the gate dielectric until the second junction field-effect region, a portion of the p-type well and a portion of the p-type heavily doped region are reached; a plurality of gate openings passing through the interlayer dielectric to the gate electrode; a first metal layer disposed at the bottom side of the source opening to form an ohmic contact with a portion of the n-type heavily doped region and a portion of the p-type heavily doped region; and a second metal layer comprising a first portion and a second portion, wherein the first portion covers the source openings and is electrically connected to the first metal layer;
the first portion covers the junction openings to faun a Schottky contact with the second junction field-effect region; and
the second portion covers the gate openings and is electrically insulated from the first portion. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
-
Specification